a65e0c6a7f14d80e87b82959c7333595cbd3e54e |
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27-Jan-2014 |
Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> |
clk: keystone: gate: fix clk_init_data initialization The clk_init_data struct is allocated in the stack. All members of this struct should be initialized before using otherwise it will lead to unpredictable situation as it can contain garbage. Ultimately the clk->flag field contains garbage. In my case it leads that flag CLK_IGNORE_UNUSED is set for most of clocks. As result a bunch of unused clocks cannot be disabled. So initialize flags in this structure too. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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e0c223ec67a98f70770eec85e625015f5af69f10 |
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23-Nov-2013 |
Grygorii Strashko <grygorii.strashko@ti.com> |
clk: keystone: gate: fix error handling on init This patch fixes Keystone gate control clock driver initialization path: 1) clk_register_psc() returns error code and not a pure pointer, hence its return value need to be checked using IS_ERR(clk) macro. 2) Mapped IO memory isn't unmapped in case of errors, hence fix it. Cc: Mike Turquette <mturquette@linaro.org Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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7affe5685c962ed0bc0fadf307400484b2276c89 |
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26-Sep-2013 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
clk: keystone: Add gate control clock driver Add the driver for the clock gate control which uses PSC (Power Sleep Controller) IP on Keystone 2 based SOCs. It is responsible for enabling and disabling of the clocks for different IPs present in the SoC. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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