| 7d155dacc1699a3ceae26b69808a1d3199394469 |
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12-Jun-2014 |
Ben Skeggs <bskeggs@redhat.com> |
drm/gk208-/gr: stop touching 0x260 inappropriately
As a side note.. It's a bit hard to figure out how to name this commit..
GK20A is NVEA, which is before NV108 (GK208).. Confusing.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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| 420b94697722512a2c0732970dc1530197a49adb |
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17-Feb-2014 |
Alexandre Courbot <acourbot@nvidia.com> |
support for platform devices
Upcoming mobile Kepler GPUs (such as GK20A) use the platform bus instead
of PCI to which Nouveau is tightly dependent. This patch allows Nouveau
to handle platform devices by:
- abstracting PCI-dependent functions that were typically used for
resource querying and page mapping,
- introducing a nv_device_is_pci() function that allows to make
PCI-dependent code conditional,
- providing a nouveau_drm_platform_probe() function that takes a GPU
platform device to be probed.
Core code as well as engine/subdev drivers are updated wherever possible
to make use of these functions. Some older drivers are too dependent on
PCI to be properly updated, but all newer code on which future chips may
depend should at least be runnable with platform devices.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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| fa8c9ac72fe0bcdf5bc7cc84e85cc2a1af53f9fd |
|
05-Feb-2014 |
Ilia Mirkin <imirkin@alum.mit.edu> |
drm/nv4c/mc: nv4x igp's have a different msi rearm register
See https://bugs.freedesktop.org/show_bug.cgi?id=74492
Reported-by: Ronald <ronald645@gmail.com>
Suggested-by: Marcin Kościelnicki <koriakin@0x04.net>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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| 9a9d5c64ef8b744a50446a0467aaf49a3292ddff |
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14-Oct-2013 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nv50-nv86,nv92/mc: rearm msi via pci config space, rather than mmio mirror
This is what NVIDIA do on these chipsets, let's hope it works around
the reported MSI failures for us on NV86.
v2: updated to include G92, as per information provided by NVIDIA.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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| 1b4fea0f6a2167669f429771838946864ffdf9b0 |
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11-Oct-2013 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nvc0,nvc4/mc: handle 0xc0's "special" msi rearm
v2. updated to cover GF104, as per information provided by NVIDIA.
Reported-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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| 08f6fbdb9bef0f9f920a8531addb0952c293d4c9 |
|
11-Oct-2013 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/mc: store static data in nouveau_mc class definition
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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| a27e56996687e79416d69a7e6dc26f9d8fe06059 |
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28-Aug-2013 |
Lucas Stach <dev@lynxeye.de> |
drm/nouveau: use MSI interrupts
MSIs were only problematic on some old, broken chipsets. But now that we
already see systems where PCI legacy interrupts are somewhat flaky, it's
really time to move to MSIs.
v2 (Ben Skeggs): blacklist BR02 boards
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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| 6ff8c76a566f823d796359a6c1d76b7668f1e34d |
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21-Aug-2013 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/mc: fix race condition between constructor and request_irq()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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| 0fa9061ae8c10a9178d696cf48d94c3bf2848f9f |
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22-Mar-2013 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/mc: handle irq-related setup ourselves
We need to be able to process interrupts before the DRM code is able to
actually enable them, set it up ourselves. Also, it's less convoluted
to *not* use the DRM wrappers it appears...
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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| 7d9115dee978e8540734c456c925d71a37752b8d |
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11-Jul-2012 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/mc: port to subdev interfaces
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
|