| b397207b7475afa9df2f94541f978100ff1ea47e |
|
02-Jul-2014 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/cik: fix typo in EOP packet
Volatile bit was in the wrong location. This bit is
not used at the moment.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
|
| 1c89d27fb9f169003c5a82561ffeb8adb980ebfb |
|
10-May-2014 |
Christian König <christian.koenig@amd.com> |
drm/radeon: add proper support for RADEON_VM_BLOCK_SIZE v2
This patch makes it possible to decide how many address
bits are spend on the page directory vs the page tables.
v2: remove unintended change
Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| f5d636d2a74b755879feec35e14a259de52ccc07 |
|
23-Apr-2014 |
Christian König <christian.koenig@amd.com> |
drm/radeon: use pflip irq on R600+ v2
Testing the update pending bit directly after issuing an
update is nonsense cause depending on the pixel clock the
CRTC needs a bit of time to execute the flip even when we
are in the VBLANK period.
This is just a non invasive patch to solve the problem at
hand, a more complete and cleaner solution should follow
in the next merge window.
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=76564
v2: fix source IDs for CRTC2-6
Signed-off-by: Christian König <christian.koenig@amd.com>
Cc: stable@vger.kernel.org
|
| b9fa18837610483b09a07f1419e6b9f333c46023 |
|
05-Sep-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: add support for vce 2.0 clock gating
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| 5ad6bf91ef8fd265aee252982a7d6fcf78436153 |
|
22-Aug-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: fill in set_vce_clocks for CIK asics
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| d93f79376f210e0b19da57a3dc841ba332daa9d0 |
|
23-May-2013 |
Christian König <christian.koenig@amd.com> |
drm/radeon: initial VCE support v4
Only VCE 2.0 support so far.
v2: squashing multiple patches into this one
v3: add IRQ support for CIK, major cleanups,
basic code documentation
v4: remove HAINAN from chipset list
Signed-off-by: Christian König <christian.koenig@amd.com>
|
| 0279ed19bd962434d334f5eeb16d14fdd9459a00 |
|
02-Oct-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: implement pci config reset for CIK (v3)
pci config reset is a low level reset that resets
the entire chip from the bus interface. It can
be more reliable if soft reset fails.
v2: fix rebase
v3: hide behind module parameter
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| fc821b70b0e58908e94464d0479c9898dd1074f9 |
|
08-Aug-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: update rb setup for hawaii
The formula needs to be adjusted since there are 4 RBs
per SH rather than 2 as on previous asics.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| 21e438af6413496a970e491cb4b3e7449f452a10 |
|
06-Aug-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: update cik_tiling_mode_table_init() for hawaii
Hawaii uses a different tiling configuration. Add support
for it.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| 939c0d3c08124cd7707168525c47354952c62d8d |
|
01-Oct-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: minor updates to cik.c for hawaii
Skip programming a register that was removed and
adjust the mask of the VM client status.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| b496038bd4d5cc5271e962e00e93767a385ff646 |
|
06-Aug-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: update cik_gpu_init() for hawaii
This adds the hawaii asic specific configuration
details.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| c9dbd70552feabc6c0455e4a9bdb7d8fdacad31e |
|
01-Oct-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: implement blit copy callback for CIK
Uses the CP ring rather than the DMA ring. Useful
for debugging and benchmarking.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| 134b480f4b92654b9590fad6c9374c7dc6722375 |
|
23-Sep-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: Add support for programming the FMT blocks
The FMT blocks control how data is sent from the backend
of the display pipe to to monitor. Proper set up of the
FMT blocks are required for 30bpp formats. Additionally,
dithering can be enabled on for better display with 18 and
24bpp displays. The exception is LVDS/eDP which atom
takes care of in the SelectCRTC_Source table. For now
just enable truncation until we test dithering more.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| bc01a8c7a24169f8b111b7dda6f5d8e7088309af |
|
19-Aug-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: update line buffer allocation for dce8
We need to allocate line buffer to each display when
setting up the watermarks. Failure to do so can lead
to a blank screen. This fixes blank screen problems
on dce8 asics.
Based on an initial fix from:
Jay Cornwall <jay.cornwall@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
|
| 473359bc28e193031a76d99f71e8b6c4808719a6 |
|
09-Aug-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: restructure cg/pg on cik (v2)
- use new cg/pg flags for finer grained clock and
powergating control
- restructure the cg/pg code so it can be called from
other components such as dpm
v2: fix build breakage from rebase
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| ae3e40e8712414321ef2b61e8bb26a5d9701643b |
|
18-Jul-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/dpm: add debugfs support for KB/KV
This allows you to look at the current DPM state via
debugfs.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| 94b4adc5ae30fb451300bdca901ae9771f6baf5f |
|
15-Jul-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/dpm: add debugfs support for CI
This allows you to look at the current DPM state via debugfs.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| cc8dbbb4f62aa53e604e7c61dedc03ee4e8dfed4 |
|
14-Aug-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: add dpm support for CI dGPUs (v2)
This adds dpm support for btc asics. This includes:
- dynamic engine clock scaling
- dynamic memory clock scaling
- dynamic voltage scaling
- dynamic pcie gen switching
Set radeon.dpm=1 to enable.
v2: remove unused radeon_atombios.c changes,
make missing smc ucode non-fatal
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| 41a524abff2630dce0f9c38eb7340fbf2dc5bf27 |
|
14-Aug-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/kms: add dpm support for KB/KV
This adds dpm support for KB/KV asics. This includes:
- dynamic engine clock scaling
- dynamic voltage scaling
- power containment
- shader power scaling
Set radeon.dpm=1 to enable.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| 286d9cc67a87863ba510b22d3f32cbeed9864b85 |
|
21-Jun-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: add get_temperature() callbacks for CIK (v2)
This added support for the on-chip thermal sensors on
CIK asics.
v2: fix register offset.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| a412fce0548105f14e48d25094d98fc87f7c0df4 |
|
23-Apr-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/cik: add rlc helpers for DPM
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| 22c775ce80ed921fe9490f3cc2ca66dcda44f572 |
|
23-Jul-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: implement clock and power gating for CIK (v3)
Only the APUs support power gating.
v2: disable cgcg for now
v3: workaround hw issue in mgcg
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| 866d83de0c9cc36a598252282bdedc158f50dcc2 |
|
15-Apr-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/cik: restructure rlc setup
Restructure rlc setup to handle clock and power
gating.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| 7235711a43b6839f5759327d003fa334c4a703f2 |
|
04-Apr-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: add support for ASPM on CIK asics
Enables PCIE ASPM (Active State Power Management) on
CIK asics.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| 8a7cd27679d0451c7cf072af70acce51d15c446d |
|
06-Aug-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/cik: add support for pcie gen1/2/3 switching
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| 3ec7d11b9a8f280cd68e53d4a7877624cc002e43 |
|
14-Jun-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: add fault decode function for CIK
Helpful for debugging GPUVM errors as we can see what
hw block and page generated the fault in the log.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| 963e81f9e060113d3bec1aa95eac76a7d3810879 |
|
26-Jun-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/cik: Add support for compute queues (v4)
On CIK, the compute rings work slightly differently than
on previous asics, however the basic concepts are the same.
The main differences:
- New MEC engines for compute queues
- Multiple queues per MEC:
- CI/KB: 1 MEC, 4 pipes per MEC, 8 queues per pipe = 32 queues
- KV: 2 MEC, 4 pipes per MEC, 8 queues per pipe = 64 queues
- Queues can be allocated and scheduled by another queue
- New doorbell aperture allows you to assign space in the aperture
for the wptr which allows for userspace access to queues
v2: add wptr shadow, fix eop setup
v3: fix comment
v4: switch to new callback method
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
|
| 87167bb16dfdd76b836ed3c19024c4a2d985f993 |
|
09-Apr-2013 |
Christian König <christian.koenig@amd.com> |
drm/radeon: add UVD support for CIK (v3)
v2: agd5f: fix clock dividers setup for bonaire
v3: agd5f: rebase
Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| 6e2c3c0ae70ccac2e8d8f2c932e72fe9866930ca |
|
04-Apr-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/cik: add pcie_port indirect register accessors
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| 2c67912c439ca501c7a23d69183bf71eab167d35 |
|
09-Apr-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: add get_xclk() callback for CIK
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| cc066715e6e164032ab382625cd311079a2f90ac |
|
09-Apr-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: update CIK soft reset
Update to the newer programming model.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| 44fa346f7ac0e23a53ae0a5587d14ef1c3f86647 |
|
19-Dec-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: add get_gpu_clock_counter() callback for cik
Used for GPU clock counter snapshots.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| cd84a27d188b0b5f53f5782d02695e7d25517afc |
|
20-Jul-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/dce8: add support for display watermark setup
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| 21a93e130d4b3b8c6a45fa27d2678e91ad2ace7d |
|
09-Apr-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/cik: add support for sDMA dma engines (v8)
CIK has new asynchronous DMA engines called sDMA
(system DMA). Each engine supports 1 ring buffer
for kernel and gfx and 2 userspace queues for compute.
TODO: fill in the compute setup.
v2: update to the latest reset code
v3: remove ib_parse
v4: fix copy_dma()
v5: drop WIP compute sDMA queues
v6: rebase
v7: endian fixes for IB
v8: cleanup for release
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| 9d97c99b1846c26102ddd1fac515b5783ce11253 |
|
06-Sep-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/cik: log and handle VM page fault interrupts
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| a59781bbe528a0c2b0468d8baeea88a61d8b7e3c |
|
09-Nov-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: add support for interrupts on CIK (v5)
Todo:
- handle interrupts for compute queues
v2: add documentation
v3: update to latest reset code
v4: update to latest illegal CP handling
v5: fix missing break in interrupt handler switch statement
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| f6796caee6fc0f97e8d38f5b8b060ab1433ae54e |
|
09-Nov-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: Add support for RLC init on CIK (v4)
RLC handles the interrupt controller and other tasks
on the GPU.
v2: add documentation
v3: update programming sequence
v4: additional setup
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| 2cae3bc3f37815b687e9ac2b304d5ca82f806f4c |
|
05-Jul-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: add IB and fence dispatch functions for CIK gfx (v7)
For gfx ring only. Compute is still todo.
v2: add documentation
v3: update to latest reset changes, integrate emit update patch.
v4: fix count on wait_reg_mem for HDP flush
v5: use old hdp flush method for fence
v6: set valid bit for IB
v7: cleanup for release
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| 841cf442fd5326683db87e9e4f8050a47d2446da |
|
19-Dec-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: Add CP init for CIK (v7)
Sets up the GFX ring and loads ucode for GFX and Compute.
Todo:
- handle compute queue setup.
v2: add documentation
v3: integrate with latest reset changes
v4: additional init fixes
v5: scratch reg write back no longer supported on CIK
v6: properly set CP_RB0_BASE_HI
v7: rebase
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| bc8273fe97019e0cd1cdc893c6b40c0add7e8de3 |
|
30-Jun-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: add support mc ucode loading on CIK (v2)
Load the GDDR5 ucode and train the links.
v2: update ucode
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| a00024b03dbfe9dfcd2ecbb5a508e59fec6fdf82 |
|
18-Sep-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/cik: stop page faults from hanging the system (v2)
Redirect invalid memory accesses to the default page
instead of locking up the memory controller.
v2: rebase on top of 2 level PTs
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| 1c49165d0abaad5ae4d506635d836e495d5bce43 |
|
09-Apr-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: add support for MC/VM setup on CIK (v6)
The vm callbacks are the same as the SI ones right now
(same regs and bits). We could share the SI variants, and
I may yet do that, but I figured I would add CIK specific
ones for now in case we need to change anything.
V2: add documentation, minor fixes.
V3: integrate vram offset fixes for APUs
V4: enable 2 level VM PTs
V5: index SH_MEM_* regs properly
V6: add ib_parse()
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| 6f2043ce15f0de02749ab228c2d11169b580a304 |
|
09-Apr-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: Add support for CIK GPU reset (v2)
v2: split soft reset into compute and gfx. Still need
to make reset more fine grained, but this should be a
start.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| 8cc1a5328b7406063812e3341e8f02718b54e3bc |
|
09-Apr-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: add gpu init support for CIK (v9)
v2: tiling fixes
v3: more tiling fixes
v4: more tiling fixes
v5: additional register init
v6: rebase
v7: fix gb_addr_config for KV/KB
v8: drop wip KV bits for now, add missing config reg
v9: fix cu count on Bonaire
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|