History log of /drivers/pinctrl/Kconfig
Revision Date Author Comments
e4742d5769e7f502f1b928b759ddecabf03375d7 24-Sep-2014 Uwe Kleine-König <u.kleine-koenig@pengutronix.de> pinctrl: bcm281xx: make Kconfig dependency more strict

This driver is only useful on BCM281xx, so let the driver depend on
ARCH_BCM_MOBILE but allow compile coverage testing.
The main benefit is that the driver isn't available to be selected for
machines that don't have the matching hardware.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Sherman Yin <syin@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
edad3b2a57082f6166b4f13445f70e8d3fc415fb 03-Sep-2014 Linus Walleij <linus.walleij@linaro.org> pinctrl: imx/mxs: move freescale drivers to subdir

This moves all the Freescale-related drivers (i.MX and MXS) to
its own subdirectory to clear the view.

Cc: Alexander Shiyan <shc_work@mail.ru>
Cc: Anson Huang <b20788@freescale.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Denis Carikli <denis@eukrea.com>
Cc: Markus Pargmann <mpa@pengutronix.de>
Cc: Greg Ungerer <gerg@uclinux.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
4f671cb25e0a1d2b903d9a19e66fa193572424cf 27-Jul-2014 Alexander Shiyan <shc_work@mail.ru> pinctrl: Add i.MX21 pincontrol driver

This patch adds pincontrol driver for Freescale i.MX21 SOCs.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Acked-by: Shawn Guo <shawn.guo@freescale.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
e1ee5c578fb1fa24b7ccaf1a11237a2bd70b6f9a 25-Jul-2014 Mika Westerberg <mika.westerberg@linux.intel.com> pinctrl: baytrail: Convert to use gpiolib irqchip

Instead of open-coding irqchip handling in the driver we can take advantage
of the new irqchip helpers provided by the gpiolib core.

While doing this we also make sure that we call gpiochip_irqchip_add()
after the gpiochip itself is registered as required.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
3a19805920f1b07401ea8a3ca00d7568dc2ce5e9 11-Jul-2014 Linus Walleij <linus.walleij@linaro.org> pinctrl: nomadik: move all Nomadik drivers to subdir

We have a bunch of Nomadik family pin control drivers, so let's
move them into their own subdirectory.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
dc0a3938668706f3a63cde4ceb431e9189fb2a0a 19-Jun-2014 Thierry Reding <treding@nvidia.com> pinctrl: Add NVIDIA Tegra XUSB pad controller support

The XUSB pad controller found on NVIDIA Tegra SoCs provides several pads
that lanes can be assigned to in order to support a variety of interface
options: USB 2.0, USB 3.0, PCIe and SATA.

In addition to the pin controller used to assign lanes to pads two PHYs
are exposed to allow the bricks for PCIe and SATA to be powered up and
down by PCIe and SATA drivers.

Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
ebe629a39e04db3fe876d34833a2d8a6a6d4c134 10-Jul-2014 Sachin Kamat <sachin.kamat@samsung.com> pinctrl: samsung: Group all drivers in a sub-dir

Group all pin control drivers of Samsung platform together in
a sub-directory for easy maintenance.

Signed-off-by: Sachin Kamat <sachin.kamat@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
69b78b8de65b28f65f2e31029462521855c7c351 09-Jul-2014 Linus Walleij <linus.walleij@linaro.org> pinctrl: msm: move all qualcomm drivers to subdir

We have four Qualcomm-related pin control drivers, and now there
are drivers coming in for the PMICs on these systems, so let's
create a qcom subdirectory to hold all the Qualcomm stuff.

Acked-by: Ivan T. Ivanov <iivanov@mm-sol.com>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
14d40ff8f8b25a1ae6a273b62e239c7064e5bc9f 09-Jul-2014 Bjorn Andersson <bjorn.andersson@sonymobile.com> pinctrl: msm: Add msm8960 definitions

Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
4877e51ed791ac0098471d547f9f8f84c147e1c6 03-Jun-2014 Alexander Shiyan <shc_work@mail.ru> pinctrl: Add i.MX1 pincontrol driver

This patch adds pincontrol driver for Freescale i.MX1 SOCs.

Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
244e95a7ad6a34278aa9c21677785093188d3fc8 03-Jun-2014 Uwe Kleine-König <u.kleine-koenig@pengutronix.de> pinctrl: hide CONFIG_PINMUX and CONFIG_PINCONF

These symbols are supposed to be selected by the drivers actually needing
them. The only situation where it would make sense to enable them without a
driver selecting them is when an out-of-tree pinctrl driver is used or
for compile testing.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2cc140fe360732bc5467df3ad932685c76078dd4 12-May-2014 Anson Huang <b20788@freescale.com> pinctrl: add pinctrl driver for imx6sx

Add a pinctrl driver for i.MX6 SoloX based on pinctrl-imx core
driver.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
cdcb0ab63052b0b509013abfb9be1cc9175767f1 29-Apr-2014 Linus Walleij <linus.walleij@linaro.org> pinctrl: msm: switch to using generic GPIO irqchip helpers

This switches the Qualcomm MSM pin control driver over to using
the generic GPIO irqchip helpers.

Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Josh Cartwright <joshc@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
3de68d331c24e8136da147801c2d090c3038eb32 19-May-2014 Antoine Tenart <antoine.tenart@free-electrons.com> pinctrl: berlin: add the core pinctrl driver for Marvell Berlin SoCs

The Marvell Berlin boards have a group based pinmuxing mechanism. This
adds the core driver support. We actually do not need any information
about the pins here and only have the definition of the groups.

Let's take the example of the uart0 pinmuxing on the BG2Q. Balls BK4 and
BH6 are muxed to respectively UART0 RX and TX if the group GSM12 is set
to mode 0:

Group Modes Offset Base Offset LSB Bit Width
GSM12 3 sm_base 0x40 0x10 0x2

Ball Group Mode 0 Mode 1 Mode 2
BK4 GSM12 UART0_RX IrDA0_RX GPIO9
BH6 GSM12 UART0_TX IrDA0_TX GPIO10

So in order to configure BK4 -> UART0_TX and BH6 -> UART0_RX, we need
to set (sm_base + 0x40 + 0x10) &= ff3fffff.

As pin control registers are part of either chip control or system
control registers, that deal with a bunch of other functions we rely
on a regmap instead of exclusively remapping any resources.

Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
751a99aba47e9bd30b4fd5bf36f4e0143d3e81bb 05-May-2014 Heiko Stübner <heiko@sntech.de> pinctrl: rockchip: use regmaps instead of raw mappings

This allows us to use syscons in the future.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
5f9107774fc81eb7a33ac7a2c296523ce5fbb14a 18-Apr-2014 Maxime Ripard <maxime.ripard@free-electrons.com> pinctrl: sunxi: Move the Allwinner pinctrl driver to its own directory

This will allow to create numerous files without crippling the main pinctrl
directory.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7420d2d09b1279996e06efa6792f9f13c1863b1e 15-Apr-2014 Linus Walleij <linus.walleij@linaro.org> pinctrl: sirf: switch driver to use gpiolib irqchip helpers

This switches the SiRF pinctrl driver over to using the gpiolib
irqchip helpers simplifying some of the code.

Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
b4da6573e7e2f8bd54abdb3e78a7b1d61c34d6f3 15-Apr-2014 Andy Gross <agross@codeaurora.org> pinctrl: qcom: Add definitions for IPQ8064

This adds pinctrl definitions for the GPIO pins of the TLMM v2 block in the
Qualcomm IPQ8064 platform.

Signed-off-by: Andy Gross <agross@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
80cc37329d9bef6e2b0bcf2028b04d049bd4bd90 15-Apr-2014 Alexander Stein <alexanders83@web.de> pinctrl/at91: convert driver to use gpiolib irqchip

This converts the AT91 pin control driver to register its
chained irq handler and irqchip using the helpers in the
gpiolib core.

Signed-off-by: Alexander Stein <alexanders83@web.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
fb95a94b04e268222ff76c5284af920c5e048c5c 01-Apr-2014 Uwe Kleine-König <u.kleine-koenig@pengutronix.de> pinctrl: msm8x74: make Kconfig dependency more strict

This driver is only useful on MSM8x74, so let the driver depend on
ARCH_QCOM but allow compile coverage testing.
The main benefit is that the driver isn't available to be selected for
machines that don't have the matching hardware.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
e2c802be589bf262fe8f1bd83a79111bd3873972 31-Mar-2014 Bjorn Andersson <bjorn.andersson@sonymobile.com> pinctrl: msm: Add definitions for the APQ8064 platform

This adds pinctrl definitions for the GPIO pins of the TLMM v2 block in the
Qualcomm APQ8064 platform.

Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
130cbe3082a1d69e7009b8c1dabb44babedd9269 08-Apr-2014 Linus Walleij <linus.walleij@linaro.org> pinctrl: st: use gpiolib irqchip helpers

This lets the gpiolib core handle the irqchip set-up and
chained IRQ on the primary (behind the mux) IRQ chip in
the st pinctrl driver.

Default irq type is set to level low at irqchip add time.

The v1 was sent by Linus
(https://lkml.org/lkml/2014/4/4/287).

Two changes were necessary to make it to work properly
on STiH416:
1 - dev reference was not passed to the gpio_chip
struct, causing a panic.
2 - gpiochip_irqchip_add passed IRQ_TYPE_NONE as
default type, which caused lot of warnings at
init time. I choose IRQ_TYPE_LEVEL_LOW as default.

Cc: Srinivas Kandagatla <srinivas.kandagatla@gmail.com>
Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Maxime COQUELIN <maxime.coquelin@st.com>
7418b5cc81185e4ae1fec66156c464eb0b8d8f5a 03-Apr-2014 Sherman Yin <syin@broadcom.com> pinctrl: Rename Broadcom Capri pinctrl driver

To be consistent with other Broadcom drivers, the Broadcom Capri pinctrl
driver and its related CONFIG option are renamed to bcm281xx.

Devicetree compatible string and binding documentation use
"brcm,bcm11351-pinctrl" to match the machine binding here:
Documentation/devicetree/bindings/arm/bcm/bcm11351.txt

This driver supports pinctrl on BCM11130, BCM11140, BCM11351, BCM28145
and BCM28155 SoCs.

Signed-off-by: Sherman Yin <syin@broadcom.com>
Reviewed-by: Matt Porter <mporter@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
523dcce72c72e829b9d391f8020277038c6aab82 25-Mar-2014 Linus Walleij <linus.walleij@linaro.org> pinctrl: coh901: convert driver to use gpiolib irqchip

This converts the COH901 pin control driver to register its
chained irq handler and irqchip using the helpers in the
gpiolib core.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
e0bc34a3dada03a48ff5501381ff7fdef885ed25 25-Mar-2014 Linus Walleij <linus.walleij@linaro.org> pinctrl: nomadik: convert driver to use gpiolib irqchip

This converts the Nomadik pin control driver to register its
chained irq handler and irqchip using the helpers in the
gpiolib core.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
5f2449d0228048a4c7103672187126c5c7d78d08 07-Mar-2014 Stephen Boyd <sboyd@codeaurora.org> pinctrl: msm: Drop OF_IRQ dependency

This driver doesn't rely on any functionality living in
drivers/of/irq.c to compile. Drop this dependency.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
5ba341604a054294aeb812603349bba024d716ee 24-Feb-2014 Josh Cartwright <joshc@codeaurora.org> pinctrl: msm: make PINCTRL_MSM bool instead of tristate

Modular builds of pinctrl-msm break due to handle_bad_irq being
unexported for module use. For now, make PINCTRL_MSM 'bool'.

Signed-off-by: Josh Cartwright <joshc@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
fe0ec0ee07208027e3e36a1dc4a653780b4984f2 16-Jan-2014 Linus Walleij <linus.walleij@linaro.org> pinctrl: capri: add dependency on OF

As this driver is using pinconf_generic_dt_node_to_map_pin() it
needs to depend on OF so as not to cause build problems on
archs that do not support OF.

Cc: Sherman Yin <syin@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
54b1aa5a5b166f3e0863adde6cf9d14442fa244c 21-Dec-2013 Sherman Yin <syin@broadcom.com> ARM: pinctrl: Add Broadcom Capri pinctrl driver

Adds pinctrl driver for Broadcom Capri (BCM281xx) SoCs.

v4: - PINCTRL selected in Kconfig, PINCTRL_CAPRI selected in bcm_defconfig
- make use of regmap
- change CAPRI_PIN_UPDATE from macro to inline function.
- Handle pull-up strength arg in Ohm instead of enum
v3: Re-work driver to be based on generic pin config. Moved config selection
from Kconfig to bcm_defconfig.
v2: Use hyphens instead of underscore in DT property names.

Signed-off-by: Sherman Yin <syin@broadcom.com>
Reviewed-by: Christian Daudt <bcm@fixthebug.org>
Reviewed-by: Matt Porter <matt.porter@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
376f413a7d98f02e8253cf9dd44935a7545fcb62 15-Dec-2013 Bjorn Andersson <bjorn.andersson@sonymobile.com> pinctrl: msm: Update Kconfig for PINCTRL_MSM8X74

Add GPIOLIB and OF as dependencies for PINCTRL_MSM8X74, to fix
build errors from i386-randconfig.
Also add help text and make the entries tristate, while touching
these entries.

Cc: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
[Rebased on top of pin control development branch]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
1a16bee6bce39ca31724cf928dce19bd48d78df5 09-Dec-2013 Ashwini Ghuge <aghuge@nvidia.com> pinctrl: tegra: add pinmux controller driver for Tegra124

This adds a driver for the Tegra124 pinmux, and required
parameterization data for Tegra124.

The driver uses the common Tegra pincontrol driver utility
functions to implement the majority of the driver.

This driver is not compatible with the earlier NVIDIA's SoCs,
hence add new compatibile as "nvidia,tegra124-pinmux".

Originally written by Ashwini Gguhe.
Thierry:
- Cleanups in patches.
ldewangan:
- Fix some entries for groups.
- Fix MUX enums and group sequence.

Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
CC: Thierry Reding <treding@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
0a7c0e0cdb82483a8b4998dfdff847d7a515f020 09-Dec-2013 Linus Walleij <linus.walleij@linaro.org> pinctrl: make the MSM SoC driver depend on OF

We had a compilation failure on x86_64 due to missing OF support
as this was an implicit dependency. Add an explicit dependency
on OF and OF_IRQ on the SoC driver.

Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
18334c8e18b2cea1c5c1ad4103ea1bf359a21775 09-Dec-2013 Linus Walleij <linus.walleij@linaro.org> pinctrl: make the MSM SoC driver depend on OF

We had a compilation failure on x86_64 due to missing OF support
as this was an implicit dependency. Add an explicit dependency
on OF and OF_IRQ on the SoC driver.

Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v2->v3:
- Total failure with older approaches: what we need to do is
have the *SoC subdriver* depend on OF and OF_IRQ. This is
because the placeholder bool PINCTRL_MSM cannot cascade its
dependencies when a subdriver selects it, Kconfig is smart
but not that smart.
ChangeLog v1->v2:
- OK so "depends on OF" did not work here let's try to simply
select OF and OF_IRQ for this then? It's one of those
"warning: (PINCTRL_MSM8X74) selects PINCTRL_MSM which has
unmet direct dependencies (PINCTRL && OF)" that I simply
cannot find my way out of :-/
55aaf8342db44c1d0d8bb911c50774f6eaeefbf3 06-Dec-2013 Bjorn Andersson <bjorn.andersson@sonymobile.com> pinctrl: Add msm8x74 configuration

Add initial definition of parameters for pinctrl-msm for the msm8x74
platform.

Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
f365be0925729508fd8e62f8bdb504ef896cb6e0 06-Dec-2013 Bjorn Andersson <bjorn.andersson@sonymobile.com> pinctrl: Add Qualcomm TLMM driver

This adds a pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block.

Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
b4a87c9b966f71922e54a336e90b485a5fba19b8 06-Nov-2013 Denis Carikli <denis@eukrea.com> pinctrl: pinctrl-imx: add imx25 pinctrl driver

This is mostly cut and paste from the imx35 pinctrl driver.
The data was generated using sed and awk on
arch/arm/plat-mxc/include/mach/iomux-mx25.h.

Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: devicetree@vger.kernel.org
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Eric Bénard <eric@eukrea.com>
Signed-off-by: Denis Carikli <denis@eukrea.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
b9f2f2ecce737910be1333609d43c8fbbfe8e68f 16-Nov-2013 Shawn Guo <shawn.guo@linaro.org> pinctrl: imx: drop redundant OF dependency

The IMX/MXC selects USE_OF at architecture level, so the OF dependency
at individual SoC pinctrl driver level can just be dropped.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9da8312048edcf246ac1d7ab6aa0293f252de559 05-Nov-2013 Greg Ungerer <gerg@uclinux.org> pinctrl: imx50: add pinctrl support code for the IMX50 SoC

Add code to support the specific pin arrangements of the Freescale IMX50 SoC.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
e16dbf6011137343f51685c1e0c5be36a68fc501 29-Oct-2013 Markus Pargmann <mpa@pengutronix.de> pinctrl: imx27: imx27 pincontrol driver

imx27 pincontrol driver using the imx1 core driver. The DT bindings are
similar to other imx pincontrol drivers.

Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
30612cd90005d8c4a3c53c7acadcf934a46c13df 28-Oct-2013 Markus Pargmann <mpa@pengutronix.de> pinctrl: imx1 core driver

Core driver for register formats of imx1/imx21/imx27 processors.

The pins of those processors are grouped into ports. Each port has 32
pins. The pins mux configuration is controlled by registers with 1 or 2
bit per pin, depending on the specific control register.

Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
5aad0db1c1ebb0f5be79f0adbecc16a2f0259b21 15-Oct-2013 Christian Ruppert <christian.ruppert@abilis.com> pinctrl: add TB10x pin control driver

The pinmux driver of the Abilis Systems TB10x platform based on ARC700 CPUs.
Used to control the pinmux and is a prerequisite for the GPIO driver.

Signed-off-by: Christian Ruppert <christian.ruppert@abilis.com>
Signed-off-by: Pierrick Hascoet <pierrick.hascoet@abilis.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
c8ce878206076b159ee9488133aa51314570da38 02-Oct-2013 Laxman Dewangan <ldewangan@nvidia.com> pincntrl: add support for ams AS3722 pin control driver

The AS3722 is a compact system PMU suitable for mobile phones, tablets etc.

Add a driver to support accessing the GPIO, pinmux and pin configuration
of 8 GPIO pins found on the ams AS3722 through pin control driver and
gpiolib.

The driver will register itself as the pincontrol driver and gpio driver.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9d7278d0b4238575739a96f64fb14b30ed0589b5 23-Sep-2013 Sonic Zhang <sonic.zhang@analog.com> pinctrl: pinctrl-adi2: Add dependency to arch BLACKFIN in Kconfig.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
e9a03add0c6ed5341fc59ff9c76843c2888a33fa 03-Sep-2013 Sonic Zhang <sonic.zhang@analog.com> pinctrl: ADI PIN control driver for the GPIO controller on bf54x and bf60x.

The new ADI GPIO2 controller was introduced since the BF548 and BF60x
processors. It differs a lot from the old one on BF5xx processors. So,
create a pinctrl driver under the pinctrl framework.

- Define gpio ports and pin interrupt controllers as individual platform
devices.
- Register a pinctrl driver for the whole GPIO ports and pin interrupt
devices.
- Probe pint devices before port devices. Put device instances into
the global gpio and pint lists.
- Define peripheral, irq and gpio reservation bit masks for each gpio
port as runtime resources.
- Save and restore gpio port and pint status MMRs in syscore PM functions.
- Create the plug-in subdrivers to hold the pinctrl soc data for bf54x
and bf60x. Add soc data into struct adi_pinctrl. Initialize the soc data
in pin controller probe function. Get the pin groups and functions via
the soc data reference.
- Call gpiochip_add_pin_range() in gpio device probe function to register
range cross reference between gpio device and pin control device.
- Get range by pinctrl_find_gpio_range_from_pin(), find gpio_port object
by container_of() and find adi_pinctrl by pin control device name.
- Handle peripheral and gpio requests in pinctrl operation functions.
- Demux gpio IRQs via the irq_domain created by each GPIO port.

v2-changes:
- Remove unlinke() directive.

v3-changes:
- Rename struct adi_pmx to adi_pinctrl.
- Fix the comments of struct gpio_pint.
- Remove unused pin_base in struct gpio_port.
- Change pint_assign into bool type.
- Add comments about the relationship between pint device and port device
to the driver header.
- Use BIT macro to shift bit.
- Remove all bitmap reservation help functions. Inline reservation functions
into the actual code.
- Remove gpio and offset mutual reference help functions.
- Remove all help functions to find gpio_port and adi_pinctrl structs. Get
range by pinctrl_find_gpio_range_from_pin(), find gpio_port object by
container_of() and find adi_pinctrl by pin control device name.
- Pass bool type usage variable to port_setup help function.
- Separate long bit operations into several lines and add comments.
- Use debugfs to output all GPIO request information.
- Avoid to set drvdata to NULL
- Add explanation to function adi_gpio_init_int()
- Call gpiochip_add_pin_range() in gpio device probe function to register
range cross reference between gpio device and pin control device.
- Remove the reference to pin control device from the gpio_port struct.
Remove the reference list to gpio device from the adi_pinctrl struct.
Replace the global adi_pinctrl list with adi_gpio_port_list. Walk through
the gpio list to do power suspend and resume operations.
- Remove the global GPIO base from struct adi_pinctrl, define pin base in
the platform data for each GPIO port device.
- Initialize adi_pinctrl_setup in arch_initcall().
- print the status of triggers, whether it is in GPIO mode, if it is
flagged to be used as IRQ, etc in adi_pin_dbg_show().
- Create the plug-in subdrivers to hold the pinctrl soc data for bf54x
and bf60x. Add soc data into struct adi_pinctrl. Initialize the soc data
in pin controller probe function. Get the pin groups and functions via
the soc data reference.

v4-changes:
- remove useless system_state checking.
- replace dev_err with dev_warn in both irq and gpio pin cases.
- comment on relationship between irq type and invert operation.
- It is not necessary to check the reservation mode of the requested
pin in IRQ chip operation. Remove the reservation map.
- Use existing gpio/pinctrl subsystem debugfs files. Remove pinctrl-adi2
driver specific debugfs output.
- Add linkport group and function information for bf60x.
- Separate uart and ctsrts pins into 2 groups.
- Separate APAPI and alternative ATAPI pins into 2 groups.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
608a26a7bc04a39cfd7041f31ca2b2100113d14e 27-Aug-2013 Mateusz Krawczuk <m.krawczuk@partner.samsung.com> pinctrl: Add s5pv210 support to pinctrl-exynos

This patch implements pinctrl support and adds device tree bindings
for s5pv210.

Signed-off-by: Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
63ca8db757063ca1c6ea2ed74a02f8080ac64c94 22-Aug-2013 Axel Lin <axel.lin@ingics.com> pinctrl: palmas: PINCTRL_PALMAS needs to select PINMUX

Fix below build error if !PINMUX.

CC drivers/pinctrl/pinctrl-palmas.o
drivers/pinctrl/pinctrl-palmas.c:741:21: error: variable 'palmas_pinmux_ops' has initializer but incomplete type
drivers/pinctrl/pinctrl-palmas.c:742:2: error: unknown field 'get_functions_count' specified in initializer
drivers/pinctrl/pinctrl-palmas.c:742:2: warning: excess elements in struct initializer [enabled by default]
drivers/pinctrl/pinctrl-palmas.c:742:2: warning: (near initialization for 'palmas_pinmux_ops') [enabled by default]
drivers/pinctrl/pinctrl-palmas.c:743:2: error: unknown field 'get_function_name' specified in initializer
drivers/pinctrl/pinctrl-palmas.c:743:2: warning: excess elements in struct initializer [enabled by default]
drivers/pinctrl/pinctrl-palmas.c:743:2: warning: (near initialization for 'palmas_pinmux_ops') [enabled by default]
drivers/pinctrl/pinctrl-palmas.c:744:2: error: unknown field 'get_function_groups' specified in initializer
drivers/pinctrl/pinctrl-palmas.c:744:2: warning: excess elements in struct initializer [enabled by default]
drivers/pinctrl/pinctrl-palmas.c:744:2: warning: (near initialization for 'palmas_pinmux_ops') [enabled by default]
drivers/pinctrl/pinctrl-palmas.c:745:2: error: unknown field 'enable' specified in initializer
drivers/pinctrl/pinctrl-palmas.c:745:2: warning: excess elements in struct initializer [enabled by default]
drivers/pinctrl/pinctrl-palmas.c:745:2: warning: (near initialization for 'palmas_pinmux_ops') [enabled by default]
make[2]: *** [drivers/pinctrl/pinctrl-palmas.o] Error 1
make[1]: *** [drivers/pinctrl] Error 2
make: *** [drivers] Error 2

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
736658c5ebc93743687c6f627c9317b97d26c5be 19-Aug-2013 Mark Brown <broonie@linaro.org> pinctrl: palmas: Fix device name in Kconfig text

The device family is called Palmas so there should be a 's' on the end of
the name.

Signed-off-by: Mark Brown <broonie@linaro.org>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
0a8d3e2412841c6b1dab1006fd5f7ab5b689db21 06-Aug-2013 Laxman Dewangan <ldewangan@nvidia.com> pinctrl: palmas: add pincontrol driver

TI Palmas series Power Management IC have multiple pins which can be
configured for different functionality. This pins can be configured
for different function. Also their properties like pull up/down,
open drain enable/disable are configurable.

Add support for pincontrol driver Palmas series device like TPS65913,
TPS80036. The driver supports to be register from DT only.

Changes from V1:
- Add generic property for pins and functions in pinconf-generic.
- Add APIs to map the DT and subnode.
- Move common utils APIs to the pinctrl-utils from this file.
- Update the binding document accordingly.
Changes from V2:
- Add ack by Lee.
- Correct the binding docs.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
ec243320e02ca9e3cb64c0ba774e25db73b32fdb 10-Jul-2013 Andy Shevchenko <andriy.shevchenko@linux.intel.com> pinctrl-baytrail: fix indentations

There are two minor issues with indentation in the code. This patch fixes them.
No functional changes.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
701016c0cba594d5dbd26652ed1e52b0fe2926fd 20-Jun-2013 Srinivas KANDAGATLA <srinivas.kandagatla@st.com> pinctrl: st: Add pinctrl and pinconf support.

This patch add pinctrl support to ST SoCs.

About hardware:
ST Set-Top-Box parts have two blocks called PIO and PIO-mux which handle
pin configurations.

Each multi-function pin is controlled, driven and routed through the PIO
multiplexing block. Each pin supports GPIO functionality (ALT0) and
multiple alternate functions(ALT1 - ALTx) that directly connect the pin
to different hardware blocks. When a pin is in GPIO mode, Output Enable
(OE), Open Drain(OD), and Pull Up (PU) are driven by the related PIO
block. Otherwise the PIO multiplexing block configures these parameters
and retiming the signal.

About driver:
This pinctrl driver manages both PIO and PIO-mux block using pinctrl,
pinconf, pinmux, gpio subsystems. All the pinctrl related config
information can only come from device trees.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
b58f0273f0858214da2ee4e1675221e56f7712ec 20-Jun-2013 James Hogan <james.hogan@imgtec.com> pinctrl-tz1090-pdc: add TZ1090 PDC pinctrl driver

Add a pin control driver for the TZ1090's low power pins via the
powerdown controller SOC_GPIO_CONTROL registers.

These pins have individually controlled pull-up, and group controlled
schmitt, slew-rate, drive-strength, and power-on-start (pos).

The pdc_gpio0 and pdc_gpio1 pins can also be muxed onto the
ir_mod_stable_out and ir_mod_power_out functions respectively. If no
function is set they remain in GPIO mode. These muxes can be overridden
by requesting them as GPIOs.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Rob Landley <rob@landley.net>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-doc@vger.kernel.org
Cc: devicetree-discuss@lists.ozlabs.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
d5025f9f535108ba44c7f00573a2a34c18a3ea2b 20-Jun-2013 James Hogan <james.hogan@imgtec.com> pinctrl-tz1090: add TZ1090 pinctrl driver

Add a pin control driver for the main pins on the TZ1090 SoC. This
doesn't include the low-power pins as they're controlled separately via
the Powerdown Controller (PDC) registers.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Rob Landley <rob@landley.net>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-doc@vger.kernel.org
Cc: devicetree-discuss@lists.ozlabs.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
83978253d0c3e12bf81d4b5f419a0200d5cb19a6 10-Jun-2013 Doug Anderson <dianders@chromium.org> ARM: EXYNOS: Select PINCTRL_EXYNOS for exynos4/5 at chip level

Previously if you had MACH_EXYNOS5_DT but not MACH_EXYNOS4_DT you'd be
missing the pincontrol definitions. Move PINCTRL selects to the arch
level since we should be enabling the code for all exynos variants.

Update the PINCTRL descriptions to indicate that PINCTRL_EXYNOS is not
for exynos5440. Also add basic dependencies for the PINCTRL_EXYNOS
kernel config.

Signed-off-by: Doug Anderson <dianders@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
a5d811bbf1c6df86cfe23948059ea614554b9f19 18-Jun-2013 Mathias Nyman <mathias.nyman@linux.intel.com> pinctrl: add Intel BayTrail GPIO/pinctrl support

Add support for gpio on Intel BayTrail platforms. BayTrail supports 3 banks
of gpios called SCORE, NCORE ans SUS with 102, 28 and 44 gpio pins.
Supports gpio interrupts and ACPI gpio events

Pins may be muxed to alternate function instead of gpio by firmware.
This driver does not touch the pin muxing and expect firmare
to set pin muxing and pullup/down properties properly.

Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
d3e5116119bd02ea7716bbe04b39c21bba4bcf42 10-Jun-2013 Heiko Stübner <heiko@sntech.de> pinctrl: add pinctrl driver for Rockchip SoCs

This driver adds support the Cortex-A9 based SoCs from Rockchip,
so at least the RK2928, RK3066 (a and b) and RK3188.
Earlier Rockchip SoCs seem to use similar mechanics for gpio
handling so should be supportable with relative small changes.
Pull handling on the rk3188 is currently a stub, due to it being
a bit different to the earlier SoCs.

Pinmuxing as well as gpio (and interrupt-) handling tested on
a rk3066a based machine.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
78bafc66180d42f972b443b0b573a1b6ff9aa522 28-May-2013 Jingchang Lu <b35083@freescale.com> pinctrl: add VF610 pinctrl driver

Adds Freescale Vybrid VF610 pin controller
driver to IMX common pinctrl driver framework.

Signed-off-by: Jingchang Lu <b35083@freescale.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
af99a7507469d4fa6dd4d8d633e093b1ff7aff6e 20-May-2013 Heiko Stuebner <heiko@sntech.de> pinctrl: Add pinctrl-s3c24xx driver

The s3c24xx pins follow a similar pattern as the other Samsung SoCs and
can therefore reuse the already introduced infrastructure.

The s3c24xx SoCs have one design oddity in that the first 4 external
interrupts do not reside in the eint pending register but in the main
interrupt controller instead. We solve this by forwarding the external
interrupt from the main controller into the irq domain of the pin bank.
The masking/acking of these interrupts is handled in the same way.

Furthermore the S3C2412/2413 SoCs contain another oddity in that they
keep the same 4 eints in the main interrupt controller and eintpend
register and requiring ack operations to happen in both. This is solved
by using different compatible properties for the wakeup eint node which
set a property accordingly.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
21e59123a8737544bfdc547e6fbb63aef2f9d284 21-Mar-2013 Shawn Guo <shawn.guo@linaro.org> pinctrl: add pinctrl driver for imx6sl

Add a pinctrl driver for i.MX6 SoloLite based on pinctrl-imx core
driver.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
3f551d6acaacd93b143769ad52239f0f3eee4d5b 21-Mar-2013 Shawn Guo <shawn.guo@linaro.org> pinctrl: add pinctrl driver for imx6dl

The imx6dl is a derivative of imx6q with very limited difference. These
two SoCs are so compatible that they can be handled as one platform in
software. That said, we will not have target SOC_IMX6DL but just
reusing SOC_IMX6Q. That's why the pinctrl-imx6dl driver is added here
with symbol PINCTRL_IMX6Q controlling the build of it.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
61dd726131777017348b70bd8576b42994a8ffa2 18-Mar-2013 Tomasz Figa <tomasz.figa@gmail.com> pinctrl: Add pinctrl-s3c64xx driver

This patch adds pinctrl-s3c64xx driver which implements pin control
interface for Samsung S3C64xx SoCs.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
170c6152aebc5538db22dbdf56fba11ccba7a6f4 19-Feb-2013 Tony Prisk <linux@prisktech.co.nz> pinctrl: gpio: vt8500: Add pincontrol driver for arch-vt8500

This patch adds support for the GPIO/pinmux controller found on the VIA
VT8500 and Wondermedia WM8xxx-series SoCs.

Each pin within the controller is capable of operating as a GPIO or as
an alternate function. The pins are numbered according to their control
bank/bit so that if new pins are added, the existing numbering is maintained.

All currently supported SoCs are included: VT8500, WM8505, WM8650, WM8750 and
WM8850.

Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
62194200e5e383af2085faf35b6f009364446069 13-Mar-2013 Haojian Zhuang <haojian.zhuang@linaro.org> pinctrl: remove pxa pinctrl driver

pinctrl-pxa driver doesn't support well on DT mode. Now pinctrl-single
could support DT mode & pin configuration. Use pinctrl-single driver to
support MMP/PXA silicons instead.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9dddb4df90d136429b6d6ddefceb49a9b93f6cd1 17-Feb-2013 Haojian Zhuang <haojian.zhuang@linaro.org> pinctrl: single: support generic pinconf

Support the operation of generic pinconf. The supported config arguments
are INPUT_SCHMITT, INPUT_SCHMITT_ENABLE, DRIVE_STRENGHT, BIAS_DISABLE,
BIAS_PULLUP, BIAS_PULLDOWN, SLEW_RATE.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
a1ed26703e5e7db1be21177df22558370dc599e6 18-Jan-2013 Kukjin Kim <kgene.kim@samsung.com> pinctrl: exynos: change PINCTRL_EXYNOS option

Since pinctrl-exynos can support exynos4 and exynos5 so changed
the option name to PINCTRL_EXYNOS for more clarity.

Cc: Thomas Abraham <Thomas.abraham@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
a8f96e4178920b43525da7b2635b2ee3a53896b8 28-Jan-2013 Patrice Chotard <patrice.chotard@stericsson.com> pinctrl/abx500: add AB8540 sub-driver

Add AB8540 sub driver to the ABx500 family, pins, pin groups and
gpio range.

As the pin controller (also the ABx500 controllers) is an
inherent part of the SoC and will prevent boot if not
available, select this from the Ux500 SoC Kconfig.

Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Patrice Chotard <patrice.chotard@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
09dbec3f74b51af614f239d3374fd7c7752c9990 28-Jan-2013 Patrice Chotard <patrice.chotard@stericsson.com> pinctrl/abx500: add AB9540 sub-driver

Add AB9540 sub driver to the ABx500 family, pins, pin groups and
gpio range.

As the pin controller (also the ABx500 controllers) is an
inherent part of the SoC and will prevent boot if not
available, select this from the Ux500 SoC Kconfig.

Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Patrice Chotard <patrice.chotard@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
1aa2d8d4055267462f8943e2a1e6eb2e7034eb25 28-Jan-2013 Patrice Chotard <patrice.chotard@stericsson.com> pinctrl/abx500: add AB8505 sub-driver

Add AB8505 sub driver to the ABx5x family.

As the pin controller (also the ABx500 controllers) is an
inherent part of the SoC and will prevent boot if not
available, select this from the Ux500 SoC Kconfig.

Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Patrice Chotard <patrice.chotard@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
3c93799378ce0cb13179ba5a28366573028e03cf 08-Jan-2013 Patrice Chotard <patrice.chotard@st.com> pinctrl/abx500: add AB8500 sub-driver

This adds a subdriver for the AB8500 pinctrl portions.
As the pin controller (also the ABx500 controllers) is an
inherent part of the SoC and will prevent boot if not
available, select this from the Ux500 SoC Kconfig.

Acked-by: Olof Johansson <olof@lixom.net>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
0493e6493031523f78680b4469f02fc1b2d440f3 08-Jan-2013 Patrice Chotard <patrice.chotard@st.com> pinctrl: add abx500 pinctrl driver core

This adds the AB8500 core driver, which will be utilized by
the follow-on drivers for different ABx500 variants.
Sselect the driver from the DBX500_SOC, as this chip is
powering and clocking that SoC.

Cc: Samuel Ortiz <sameo@linux.intel.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
6e54d8d252ed09ae148af6565971974af9a96e10 15-Dec-2012 Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> sh-pfc: Move driver from drivers/sh/ to drivers/pinctrl/

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Paul Mundt <lethal@linux-sh.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
0e37f88d9ad800f5dd94c9fc9dc304b4e9cb7d2c 18-Jan-2013 Maxime Ripard <maxime.ripard@free-electrons.com> ARM: sunxi: Add pinctrl driver for Allwinner SoCs

The Allwinner SoCs have an IP module that handle both the muxing and the
GPIOs.

This IP has 8 banks of 32 bits, with a number of pins actually useful
for each of these banks varying from one to another, and depending on
the SoC used on the board.

This driver only implements the pinctrl part, the gpio part will come
eventually.

Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
7452b64d0154ab8ae4933b8e97feebc1ae98d1a4 18-Jan-2013 Kukjin Kim <kgene.kim@samsung.com> pinctrl: exynos: change PINCTRL_EXYNOS option

Since pinctrl-exynos can support exynos4 and exynos5 so changed
the option name to PINCTRL_EXYNOS for more clarity.

Cc: Thomas Abraham <Thomas.abraham@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
b6ae7a26535bb37c6c023c6f25b7f98904a8ab7c 08-Jan-2013 Pritesh Raithatha <praithatha@nvidia.com> pinctrl: tegra114: add pinctrl driver for NVIDIA's Tegra114 SoC

This adds a driver for the Tegra114 pinmux, and required
parameterization data for Tegra114.

The driver uses the common Tegra pincontrol driver utility
functions to implement the majority of the driver.

This driver is not compatible with the earlier NVIDIA's SoCs,
hence add new compatibile as "nvidia,tegra114-pinmux".

Originally written by Pritesh.
ldewangan:
- cleanup the patches,
- remove non-require tables.
- Use module_platform_driver() for driver registartion.

Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
f9925b5f681d16a831210f00daedf8e9105073f4 27-Dec-2012 Kukjin Kim <kgene.kim@samsung.com> pinctrl: samsung: removing duplicated condition for PINCTRL_SAMSUNG

Now, PINCTRL_SAMSUNG should be enabled with PINCTRL_EXYNOS so we don't
need to add 'depends on' condition already added in PINCTRL_EXYNOS.

Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
d279bc77b4937d176cca289cda6cff609d480d37 28-Nov-2012 Axel Lin <axel.lin@ingics.com> pinctrl: Drop selecting PINCONF for MMP2, PXA168 and PXA910

These drivers do not need to select PINCONF.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
f0b9a7e521fa2fc5f3e0e57472126a6fed9cbb99 10-Oct-2012 Thomas Abraham <thomas.abraham@linaro.org> pinctrl: exynos5440: add pinctrl driver for Samsung EXYNOS5440 SoC

Add a new pinctrl driver for Samsung EXYNOS5440 SoC. The pin controller
module in EXYNOS5440 is different from the pin controller found on other
Samsung SoC. Hence, the pin controller driver for EXYNOS5440 SoC is
independent of the Samsung pinctrl framework.

Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
cbc351abe3c9bcec11c712dd41bb212748fd46d3 15-Nov-2012 Arnd Bergmann <arnd@arndb.de> pinctrl/samsung: don't allow enabling pinctrl-samsung standalone

The main samsung pinctrl module references the specific exynos4210
pinctrl driver, which selects the main driver in Kconfig.

Making the main driver a silent "bool" option avoid this potential
build error if CONFIG_PINCTRL_SAMSUNG=y && CONFIG_PINCTRL_EXYNOS4=n:

drivers/built-in.o:(.rodata+0x4e4): undefined reference to `exynos4210_pin_ctrl'

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Tomasz Figa <t.figa@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
507ccdbfd80020c402cbbf65ceeb3235edb79021 12-Nov-2012 Axel Lin <axel.lin@ingics.com> pinctrl: tegra: Make PINCTRL_TEGRA select PINMUX && PINCONF

Then we can remove "select PINMUX && PINCONF" from PINCTRL_TEGRA{20,30}.
This simplifies the dependency.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
90db8a145c3aa5a14fda6c587e53d7f15070b4ab 12-Nov-2012 Axel Lin <axel.lin@ingics.com> pinctrl: mxs: Make PINCTRL_MXS select PINMUX && PINCONF

Then we can remove "select PINMUX && PINCONF" from PINCTRL_IMX{23,28}.
This simplifies the dependency.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
d3e26f2fe993b5dbc8b4b2275d77f9ad3e08c81a 27-Sep-2012 Barry Song <Baohua.Song@csr.com> pinctrl: sirf: enable the driver support new SiRFmarco SoC

The driver supports old up SiRFprimaII SoCs, this patch makes it support
the new SiRFmarco as well.
SiRFmarco, as a SMP SoC, adds new SIRFSOC_GPIO_PAD_EN_CLR registers, to
disable GPIO pad, we should write 1 to the corresponding bit in the new
CLEAR register instead of writing 0 to SIRFSOC_GPIO_PAD_EN.

Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
06763c741b0a19160482c9b34e5bbc3e50dba79a 24-Oct-2012 Thomas Petazzoni <thomas.petazzoni@free-electrons.com> pinctrl: mvebu: move to its own directory

Like the spear platform, the mvebu platform has multiple files: one
core file, and then one file per SoC family. More files will be added
later, as support for mach-orion5x and mach-mv78xx0 SoCs is added to
pinctrl-mvebu. For those reasons, having a separate subdirectory,
drivers/pinctrl/mvebu/ makes sense, and it had already been suggested
by Linus Wallej when the driver was originally submitted.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
55d2e40d4acf9081daee5a95d0eb474511408968 24-Oct-2012 Thomas Petazzoni <thomas.petazzoni@free-electrons.com> pinctrl: mvebu: allow plat-orion architectures to use pinctrl-mvebu

The mach-kirkwood and mach-dove architectures have not yet been
integrated into the mach-mvebu directory, which should ultimately
contain the support for all Marvell SoCs from the Engineering Business
Unit.

However, before this can happen, we need to let mach-kirkwood and
mach-dove use the pinctrl-mvebu driver, which supports the kirkwood
and dove SoC families. In order to do that, we make this driver
available as soon as PLAT_ORION is selected, instead of using
ARCH_MVEBU as a condition. In the long term, PLAT_ORION should
disappear and be fully replaced by ARCH_MVEBU, but the plan is to make
the migration step by step, by first having the existing mach-*
directories for Marvell SoCs converge on several infrastructures,
including the pinctrl one.

Also, like the spear pinctrl driver, we put all pinctrl-mvebu Kconfig
options under a if, in order to avoid having certain options
(PINCTRL_DOVE, PINCTRL_KIRKWOOD, etc.) selecting an option
(PINCTLR_MVEBU) which itself has a dependency (on ARCH_MVEBU). In this
a construct, the dependency is in fact ignored due to the selects.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
924da31416f20a8ee7a9008dd4e6e6054bc36b1b 06-Nov-2012 Axel Lin <axel.lin@ingics.com> pinctrl: samsung and exynos need to depend on OF && GPIOLIB

This patch fixes below build error when !CONFIG_OF_GPIO.

CC drivers/pinctrl/pinctrl-samsung.o
drivers/pinctrl/pinctrl-samsung.c: In function 'samsung_pinctrl_parse_dt_pins':
drivers/pinctrl/pinctrl-samsung.c:557:19: warning: unused variable 'prop' [-Wunused-variable]
drivers/pinctrl/pinctrl-samsung.c: In function 'samsung_gpiolib_register':
drivers/pinctrl/pinctrl-samsung.c:797:5: error: 'struct gpio_chip' has no member named 'of_node'
make[2]: *** [drivers/pinctrl/pinctrl-samsung.o] Error 1
make[1]: *** [drivers/pinctrl] Error 2
make: *** [drivers] Error 2

The samsung pinctrl driver supports only device tree enabled
platforms. Thus make PINCTRL_SAMSUNG depend on OF && GPIOLIB.

The reason to depend on GPIOLIB is CONFIG_OF_GPIO only available
when GPIOLIB is selected.

Since PINCTRL_EXYNOS4 select PINCTRL_SAMSUNG, thus also make
PINCTRL_EXYNOS4 depend on OF && GPIOLIB.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
6732ae5cb47c4f9a72727585956f2a5e069d1637 12-Jul-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> ARM: at91: add pinctrl support

This is also include the gpio controller as the IP share both.
Each soc will have to describe the SoC limitation and pin configuration via
DT.

This will allow to do not need to touch the C code when adding new SoC if the
IP version is supported.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
e1b2dc70cd5b00e17c703163a463d82354b1cc76 28-Sep-2012 Simon Arlott <simon@fire.lp0.eu> pinctrl: add bcm2835 driver

The BCM2835 GPIO module is a combined GPIO controller, (GPIO) interrupt
controller, and pinmux/control device.

Original driver by Simon Arlott.
Rewrite including GPIO chip device by Chris Boot.

Upstreaming changes by Stephen Warren:
* Wrote DT binding documentation.
* Changed brcm,function to an integer to more directly match the
datasheet, and to match brcm,pins being an integer.
* Implemented pull-up/down pin config.
* Removed read-only DT property and related code. The restriction this
implemented are driven by the board, not the GPIO HW block, so don't
really make sense of a HW block binding, were in general incomplete
(since they could only know about the few pins hard-coded into the
Raspberry Pi B board design and not the uncommitted GPIOS), and are
better represented simply by not writing incorrect data into pin
configuration nodes.
* Don't set GPIO_IN function select in gpio_request_enable() to avoid
glitches; defer this to gpio_set_direction(). Consequently, removed
empty bcm2835_pmx_gpio_request_enable().
* Simplified enabled_irq_map[]; make it explicitly 1 entry per bank.
* Lifted use of enabled_irq_map[] outside the per-interrupt loop in
IRQ handler, thus fixing an issue where the code was indexing into
enabled_irq_map[] by intra-bank GPIO ID, not global GPIO ID.
* Removed locking in IRQ handler, since all other code uses
spin_lock_irqsave() and so guarantees it doesn't run concurrently
with the handler.
* Moved duplicated BUILD_BUG_ON()s into probe(). Also check size of
bcm2835_gpio_pins[].
* Remove range-checking from bcm2835_pctl_get_groups_count() since we've
decided to trust the pinctrl core.
* Made bcm2835_pmx_gpio_disable_free() call bcm2835_pinctrl_fsel_set()
directly for simplicity.
* Fixed body of dt_free_map() to match latest dt_node_to_map().
* Removed GPIO ownership check from bcm2835_pmx_enable() since the pinctrl
core owns doing this.
* Made irq_chip and pinctrl_gpio_range .name == MODULE_NAME so it's more
descriptive.
* Simplified remove(); removed call to non-existent
pinctrl_remove_gpio_range(), remove early return on error.
* Don't force gpiochip's base to 0. Set gpio_range.base to gpiochip's
base GPIO number.
* Error-handling cleanups in probe().
* Switched to module_platform_driver() rather than open-coding.
* Made pin, group, and function names lower-case.
* s/broadcom/brcm/ in DT property names.
* s/2708/2835/.
* Fixed a couple minor checkpatch warnings, and other minor cleanup.

Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
Signed-off-by: Chris Boot <bootc@bootc.net>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
463e270f766aa8dd2b782d4b8bd87260eb595aa2 13-Sep-2012 Thomas Petazzoni <thomas.petazzoni@free-electrons.com> pinctrl: mvebu: add pinctrl driver for Armada XP

This pinctrl driver is not a full-blown pinctrl driver from scratch:
it relies on the common pinctrl-mvebu driver, which is used for all
Marvell EBU SoCs.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
5f597bb2be5723e1ea5d3337337f671ced4f37bf 13-Sep-2012 Thomas Petazzoni <thomas.petazzoni@free-electrons.com> pinctrl: mvebu: add pinctrl driver for Armada 370

This pinctrl driver is not a full-blown pinctrl driver from scratch:
it relies on the common pinctrl-mvebu driver, which is used for all
Marvell EBU SoCs.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
9d4b1632bcd77f7fb98c4c5c1f4f2fc70fa1aa23 13-Sep-2012 Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> pinctrl: mvebu: kirkwood pinctrl driver

This patch adds a SoC specific pinctrl driver for Marvell Kirkwood SoCs
plus DT binding documentation. This driver will use the mvebu pinctrl
driver core.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
c9f95cedfea088ec9bbcef3b8064d5275297b159 13-Sep-2012 Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> pinctrl: mvebu: dove pinctrl driver

This patch adds a SoC specific pinctrl driver for Marvell Dove SoCs
plus DT binding documentation. This driver will use the mvebu pinctrl
driver core.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
7e8d941567c99a03390154a7bb116d1b03db82b3 13-Sep-2012 Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> pinctrl: mvebu: pinctrl driver core

This patch adds a pinctrl driver core for Marvell SoCs plus DT
binding documentation. This core driver will be used by SoC family
specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

Conflicts:

arch/arm/Kconfig
e316cb2b16bbfbe48387b56e7e6b5d32ec686f82 20-May-2012 John Crispin <blogic@openwrt.org> OF: pinctrl: MIPS: lantiq: adds support for FALCON SoC

Implement support for pinctrl on lantiq/falcon socs. The FALCON has 5 banks
of up to 32 pins.

Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Cc: devicetree-discuss@lists.ozlabs.org
Cc: linux-kernel@vger.kernel.org
3f8c50c9b110dad4136ea7226cd87b0c4cdb70c8 28-Aug-2012 John Crispin <blogic@openwrt.org> OF: pinctrl: MIPS: lantiq: implement lantiq/xway pinctrl support

Implement support for pinctrl on lantiq/xway socs. The IO core found on these
socs has the registers for pinctrl, pinconf and gpio mixed up in the same
register range. As the gpio_chip handling is only a few lines, the driver also
implements the gpio functionality. This obseletes the old gpio driver that was
located in the arch/ folder.

Signed-off-by: John Crispin <blogic@openwrt.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Cc: devicetree-discuss@lists.ozlabs.org
Cc: linux-kernel@vger.kernel.org
43b169db184184e1df8dea198d454a06602c5150 06-Sep-2012 Thomas Abraham <thomas.abraham@linaro.org> pinctrl: add exynos4210 specific extensions for samsung pinctrl driver

Add information about the Exynos4210 pin banks and driver data which is
used by the Samsung pinctrl driver. In addition to this, the support for
external gpio and wakeup interrupt support is included and hooked up with
the Samsung pinctrl driver.

Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
30574f0db1b16fedf705cb792099f8a3171598eb 06-Sep-2012 Thomas Abraham <thomas.abraham@linaro.org> pinctrl: add samsung pinctrl and gpiolib driver

Add a new device tree enabled pinctrl and gpiolib driver for Samsung
SoC's. This driver provides a common and extensible framework for all
Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This
driver supports only device tree based instantiation and hence can be
used only on those Samsung platforms that have device tree enabled.

This driver is split into two parts: the pinctrl interface and the gpiolib
interface. The pinctrl interface registers pinctrl devices with the pinctrl
subsystem and gpiolib interface registers gpio chips with the gpiolib
subsystem. The information about the pins, pin groups, pin functions and
gpio chips, which are SoC specific, are parsed from device tree node.

Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
b9aa8f13eaaf65f6939c67920d2cda4399be1e2a 09-Aug-2012 Uwe Kleine-König <u.kleine-koenig@pengutronix.de> pinctrl: pinctrl-imx: add imx35 pinctrl driver

This is mostly cut'n'paste from the imx51 pinctrl driver.
The data was generated using sed and awk on
arch/arm/plat-mxc/include/mach/iomux-mx35.h.

Changes since (implicit) v1
- remove references to file names in binding documentation
- remove sed commands from comments in driver
- add explicit numbers for pins and functions

Acked-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Dong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
f79c5ed9dab3ae80f6cbe9edaafbc8a4dadb8408 10-Aug-2012 Linus Walleij <linus.walleij@linaro.org> pinctrl/nomadik: add STn8815 ASIC support

This adds support for the STN8815 ASIC for the Nomadik pin
controller.

Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
45a1b53195069f53d5cbdbfff5e5fed97004320b 20-Jul-2012 Patrice Chotard <patrice.chotard@stericsson.com> pinctrl/nomadik: add ASIC DB8450 pinctrl driver

This implements a subdriver for the DB8540 ASIC for the
Nomadik pin controller.

Signed-off-by: Patrice Chotard <patrice.chotard@stericsson.com>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
8b8b091bf07fa7ef7f13c1ac40b30bcf74050b60 10-Jul-2012 Tony Lindgren <tony@atomide.com> pinctrl: Add one-register-per-pin type device tree based pinctrl driver

Add one-register-per-pin type device tree based pinctrl driver.

This driver has been tested on omap2+ series of processors,
where there is either an 8 or 16-bit padconf register for each pin.
Support for other similar pinmux controllers can be added.

Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
3c94d1bbda491ba924e5c479e87bc2faae463253 18-Jun-2012 Linus Walleij <linus.walleij@linaro.org> pinctrl: select the proper symbol

The Kconfig entry for the COH901 pin controller depended on
PINMUX_U300 which is stale, use PINCTRL_U300 as it is called
these days.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
4f6a16bf019cb0bbe1deb7d3a83d3593dcce8706 15-May-2012 Dong Aisheng <dong.aisheng@linaro.org> pinctrl: pinctrl-imx: add imx51 pinctrl driver

ChangeLog v1->v2:
* change PIN_FUNC_ID base in binding doc to 0 from 1.

Acked-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
93fbd3c0502bd2a470ec599c870b0f8dd54ad359 15-May-2012 Dong Aisheng <dong.aisheng@linaro.org> pinctrl: pinctrl-imx: add imx53 pinctrl driver

ChangeLog v1->v2:
* change PIN_FUNC_ID base in binding doc to 0 from 1.

Acked-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
0fa7be407dc101afe2d3dc99ded99de34c967a52 15-May-2012 Arnd Bergmann <arnd@arndb.de> ARM: nomadik: enable PINCTRL_NOMADIK where needed

The nomadik gpio code has been converted to pinctrl, but the nomadik platform
still expects the old code to be present. Change it to use the new one instead.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
d41af627638a0e1e964d546e385b20650e769ce5 03-May-2012 Linus Walleij <linus.walleij@linaro.org> pinctrl/nomadik: implement pin configuration

This implements the pin configuration interface for the
Nomadik pin controller.

As part of the exercise we add a bit in the pin_cfg_t for
the Nomadik pinctrl driver that indicates if the pin should
be forced into GPIO mode. This is not done to go behind the
back of the GPIO subsystem, but to ensure that default modes
can be set by hogs on boot and system suspend/resume states.
It was used implicitly by the old code defining all config
settings and modes in a single config word but we now have
a split between pinmux and pinconf leading to the need to
have this.

We also add a bit for explicitly setting sleepmode of the
pin. This was previously handled by custom calls with the
_sleep() suffix, but we now have one single interface into
the configuration so we replace this with a bit indicating
that the pin shall be configured into sleep mode.

Some of the configuration can be refactored later to use
less custom fields on the pin_cfg_t but we are currently
leaving the old function calls in place so we stay
compatible.

ChangeLog v1->v2:
- Drop a hunk changing pinmuxing for GPIO and move it
over to the preceding pinmux patch.

Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
dbfe8ca259e1f899ca02ea33d903fa21bbea67c5 02-May-2012 Linus Walleij <linus.walleij@linaro.org> pinctrl/nomadik: implement pin multiplexing

Implements basic pinmux for the Nomadik pin controller.

The plan is to split the existing singular pin config interface
nmk_config_pin(), nmk_config_pins(), that will configure muxing
and other settings at the same time, into two interfaces
by splitting the code in pinmux and pinctrl and eventually
deleting the old interface and its helper functions when all
users are gone.

nmk_gpio_set_mode() and nmk_gpio_get_mode() are two older
interfaces for just configuring muxing/altfunctions that
will also be replaced in the end.

We take some extra care to handle the glitch-avoidance here,
but it is simpler now since there is only one altsetting per
pingroup so we know immediately if we need to avoid altfunc
C glitches for a certain group.

As part of the makeover implement the .request() and .free()
calls on the GPIO chips and have them call back into the
pinctrl layer to reserve GPIOs.

ChangeLog v1->v2:
- Rebased on pinctrl-mergebase-20120418 so we get the latest
driver infrastructure where function count is done by a fixed
value and we can drop a few range checks since this is now
handled by the core.
- Include a GPIO muxing hunk erroneously part of the pin config
patch.

Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
e98ea774c8d210364379329f042e7596f83ecc58 26-Apr-2012 Linus Walleij <linus.walleij@linaro.org> pinctrl/nomadik: basic Nomadik pinctrl interface

This adds a scratch pin control interface to the Nomadik pinctrl
driver, and defines the pins and groups in the DB8500 ASIC. We
define GPIO ranges to cover the pins exposed. The DB8500 has
more pins than this but we restrict the driver to the pins that
can be controlled from the combined GPIO and pin control hardware
to begin with.

ChangeLog v1->v2:
- Base on the latest pinctrl development from
pinctrl-mergebase-20120418 so we can get rid of legacy
group count mechanism. Also drop the range checks for group
index, this is handled by the core now.

Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
17723111e64fbcc327846ff0b33532bcf1d40f56 28-Apr-2012 Shawn Guo <shawn.guo@linaro.org> pinctrl: add pinctrl-mxs support

Add pinctrl support for Freescale MXS SoCs, i.MX23 and i.MX28.
The driver supports device tree probe only.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
d8fe35727a3c7e0f2c4ff0a579aab1d7ce252df8 27-Apr-2012 Dong Aisheng <dong.aisheng@linaro.org> pinctrl: pinctrl-imx: add imx6q pinctrl driver

Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
ae75ff8145384000e27eaa805c12e6971e3bec45 27-Apr-2012 Dong Aisheng <dong.aisheng@linaro.org> pinctrl: pinctrl-imx: add imx pinctrl core driver

The driver has mux and config support while the gpio is still
not supported.
For select input setting, the driver will handle it internally
and do not need user to take care of it.

The pinctrl-imx core driver will parse the dts file and dynamically
create the pinmux functions and groups.

Each IMX SoC pinctrl driver should register pins with a pin register map
including mux register and config register and select input map to core
for proper operations.

Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
deda8287e1a602393b052c80b815b3706987b3da 28-Mar-2012 Viresh Kumar <viresh.kumar@st.com> pinctrl: Add SPEAr pinctrl drivers

This adds pinctrl driver for SPEAr platform. It also updates MAINTAINERS file
for SPEAr pinctrl drivers.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
630e2d0494f001cc3c435cac374f92e4bde0f518 12-Apr-2012 Linus Walleij <linus.walleij@linaro.org> pinctrl: mark non-EXPERIMENTAL

With the finalization of the external driver API and the device
tree support, this subsystem is now mature and can be promoted to
non-experimental status.

Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
dc0b1aa3e2fefa6372f38d7f6d5d33581567a1b5 16-Nov-2011 Linus Walleij <linus.walleij@linaro.org> pinctrl: support pinconfig on the U300

This adds pin configuration support for the U300 driver pair,
we can now read out the biasing and drive mode in debugfs and
configure it using the new configuration API.

ChangeLog v1->v2:
- Migrate to pin config and generic pin config changes.
ChangeLog v2->v3:
- Adjust to generic pin config changes in v7 patch set.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
394349f7789fdfcdc74b61afcac84046535c40b7 24-Nov-2011 Linus Walleij <linus.walleij@linaro.org> pinctrl: introduce generic pin config

This is a split-off from the earlier patch set which adds generic
pin configuration for the pin controllers that want it. Since
we may have a system with mixed generic and custom pin controllers,
we pass a boolean in the pin controller ops vtable to indicate
if it is generic.

ChangeLog v1->v5:
- Follow parent patch versioning number system.
- Document the semantic meaning of return values from pin config
get functions, so we can iterate over pins and check their
properties from debugfs as part of the generic config code.
- Use proper cast functions in the generic debugfs pin config
file.
- Expand generic config to optionally cover groups too.
ChangeLog v5->v6:
- Update to match underlying changes.
ChangeLog v6->v7:
- Drop DRIVE_OFF parameter, use bias high impedance for this
- Delete argument for drive modes push-pull, od and os. These
are now just state transitions.
- Delete slew rate rising/falling due to discussions on on
proper semantics
- Drop config wakeup, struct irq_chip does this for now, add
back if need be.
- Set PIN_CONFIG_END to 0x7fff making room for custom config
parameters from 0x8000 and up.
- Prefix accessor functions with pinconf_
971dac7123c785fdb0d09276b5d459b67585e242 01-Feb-2012 Stephen Warren <swarren@nvidia.com> pinctrl: add a driver for NVIDIA Tegra

This adds a driver for the Tegra pinmux, and required parameterization
data for Tegra20 and Tegra30.

The driver is initially added with driver name and device tree compatible
value that won't cause this driver to be used. A later change will switch
the pinctrl driver to use the correct values, switch the old pinmux
driver to be disabled, and update all code that uses the old pinmux APIs
to use the new pinctrl APIs.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Olof Johansson <olof@lixom.net>
[squashed "fix case of Tegra30's foo_groups[] arrays"]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
f4e66983293f78e177bb210d19a46f083f5e8197 04-Jan-2012 Haojian Zhuang <haojian.zhuang@marvell.com> pinctrl: enable pinmux for mmp series

Support PXA168/PXA910/MMP2 pinmux. Now only support function switch.

Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
[Rebase and fix some whitespace issues]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
3bece55aa5356af0171aaa64fd9c4f7601c47f1c 18-Dec-2011 Linus Walleij <linus.walleij@linaro.org> pinctrl: rename U300 and SIRF pin controllers

For stringent order, rename the pinmux-* pin controllers to
pinctrl-* and also rename the Kconfig symbols and in-kernel
users.

Cc: Rongjun Ying <Rongjun.Ying@csr.com>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
ae6b4d8588f4fc95520b0e62c4b1f474c82191a9 19-Oct-2011 Linus Walleij <linus.walleij@linaro.org> pinctrl: add a pin config interface

This add per-pin and per-group pin config interfaces for biasing,
driving and other such electronic properties. The details of passed
configurations are passed in an opaque unsigned long which may be
dereferences to integer types, structs or lists on either side
of the configuration interface.

ChangeLog v1->v2:
- Clear split of terminology: we now have pin controllers, and
those may support two interfaces using vtables: pin
multiplexing and pin configuration.
- Break out pin configuration to its own C file, controllers may
implement only config without mux, and vice versa, so keep each
sub-functionality of pin controllers separate. Introduce
CONFIG_PINCONF in Kconfig.
- Implement some core logic around pin configuration in the
pinconf.c file.
- Remove UNKNOWN config states, these were just surplus baggage.
- Remove FLOAT config state - HIGH_IMPEDANCE should be enough for
everyone.
- PIN_CONFIG_POWER_SOURCE added to handle switching the power
supply for the pin logic between different sources
- Explicit DISABLE config enums to turn schmitt-trigger,
wakeup etc OFF.
- Update documentation to reflect all the recent reasoning.
ChangeLog v2->v3:
- Twist API around to pass around arrays of config tuples instead
of (param, value) pairs everywhere.
- Explicit drive strength semantics for push/pull and similar
drive modes, this shall be the number of drive stages vs
nominal load impedance, which should match the actual
electronics used in push/pull CMOS or TTY totempoles.
- Drop load capacitance configuration - I probably don't know
what I'm doing here so leave it out.
- Drop PIN_CONFIG_INPUT_SCHMITT_OFF, instead the argument zero to
PIN_CONFIG_INPUT_SCHMITT turns schmitt trigger off.
- Drop PIN_CONFIG_NORMAL_POWER_MODE and have a well defined
argument to PIN_CONFIG_LOW_POWER_MODE to get out of it instead.
- Drop PIN_CONFIG_WAKEUP_ENABLE/DISABLE and just use
PIN_CONFIG_WAKEUP with defined value zero to turn wakeup off.
- Add PIN_CONFIG_INPUT_DEBOUNCE for configuring debounce time
on input lines.
- Fix a bug when we tried to configure pins for pin controllers
without pinconf support.
- Initialized debugfs properly so it works.
- Initialize the mutex properly and lock around config tampering
sections.
- Check the return value from get_initial_config() properly.
ChangeLog v3->v4:
- Export the pin_config_get(), pin_config_set() and
pin_config_group() functions.
- Drop the entire concept of just getting initial config and
keeping track of pin states internally, instead ask the pins
what state they are in. Previous idea was plain wrong, if the
device cannot keep track of its state, the driver should do
it.
- Drop the generic configuration layout, it seems this impose
too much restriction on some pin controllers, so let them do
things the way they want and split off support for generic
config as an optional add-on.
ChangeLog v4->v5:
- Introduce two symmetric driver calls for group configuration,
.pin_config_group_[get|set] and corresponding external calls.
- Remove generic semantic meanings of return values from config
calls, these belong in the generic config patch. Just pass the
return value through instead.
- Add a debugfs entry "pinconf-groups" to read status from group
configuration only, also slam in a per-group debug callback in
the pinconf_ops so custom drivers can display something
meaningful for their pins.
- Fix some dangling newline.
- Drop dangling #else clause.
- Update documentation to match the above.
ChangeLog v5->v6:
- Change to using a pin name as parameter for the
[get|set]_config() functions, as suggested by Stephen Warren.
This is more natural as names will be what a developer has
access to in written documentation etc.
ChangeLog v6->v7:
- Refactor out by-pin and by-name get/set functions, only expose
the by-name functions externally, expose the by-pin functions
internally.
- Show supported pin control functionality in the debugfs
pinctrl-devices file.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
b4e3ac74d5cd4152f2ec6b3280b1ff3428952f7f 16-Nov-2011 Linus Walleij <linus.walleij@linaro.org> pinctrl/coh901: driver to request its pins

This makes the COH 901 driver request muxing of its GPIO pins
from the pinmux-u300 driver using the standard API calls.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
ca402d37dccf2b797440c5f03bd0db16f977acc9 16-Nov-2011 Linus Walleij <linus.walleij@linaro.org> pinctrl: move the U300 GPIO driver to pinctrl

This driver will be converted to a dual GPIO + pinctrl driver
since it supports biasing and driving control options. Hopefully
it can serve as an example.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
45f034ef205e5439a50d6f7e5f89add93131c0cc 05-Nov-2011 Linus Walleij <linus.walleij@linaro.org> pinctrl: hide subsystem from the populace

Machines that have embedded pin controllers need to select them
explicitly, so why broadcast their config options to menuconfig.
We provide a helpful submenu for those machines that do select
it, making it possible to enable debugging for example.

Reported-by: Linus Torvalds <torvalds@linux-foundation.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
393daa814f4bbc6f5c099178c073fae9f7ef6177 09-Oct-2011 Rongjun Ying <Rongjun.Ying@csr.com> pinctrl: add a driver for the CSR SiRFprimaII pinmux

This creates a pin controller driver for the SiRFprinaII
pin mux portions.

Signed-off-by: Rongjun Ying <Rongjun.Ying@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
[Fixup for changed function names and semantics in the v10 patch]
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
98da3529536ed3c78ae493f4cc3d7ac8d43fc72c 02-May-2011 Linus Walleij <linus.walleij@linaro.org> pinctrl: add a driver for the U300 pinmux

This adds a driver for the U300 pinmux portions of the system
controller "SYSCON". It also serves as an example of how to use
the pinmux subsystem. This driver also houses the platform data
for the only supported platform.

This deletes the old U300 driver in arch/arm/mach-u300 and
replace it with a driver using the new subsystem.

The new driver is considerably fatter than the old one, but it
also registers all 467 pins of the system and adds the power
and EMIF pin groups and corresponding functions. The idea
is to use this driver as a a reference for other
implementation so it needs to be as complete and verbose
as possible.

Reviewed-by: Barry Song <21cnbao@gmail.com>
[Fixup for changed function names and semantics in the v10 patch]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2744e8afb3b76343e7eb8197e8b3e085036010a5 02-May-2011 Linus Walleij <linus.walleij@linaro.org> drivers: create a pin control subsystem

This creates a subsystem for handling of pin control devices.
These are devices that control different aspects of package
pins.

Currently it handles pinmuxing, i.e. assigning electronic
functions to groups of pins on primarily PGA and BGA type of
chip packages which are common in embedded systems.

The plan is to also handle other I/O pin control aspects
such as biasing, driving, input properties such as
schmitt-triggering, load capacitance etc within this
subsystem, to remove a lot of ARM arch code as well as
feature-creepy GPIO drivers which are implementing the same
thing over and over again.

This is being done to depopulate the arch/arm/* directory
of such custom drivers and try to abstract the infrastructure
they all need. See the Documentation/pinctrl.txt file that is
part of this patch for more details.

ChangeLog v1->v2:

- Various minor fixes from Joe's and Stephens review comments
- Added a pinmux_config() that can invoke custom configuration
with arbitrary data passed in or out to/from the pinmux driver

ChangeLog v2->v3:

- Renamed subsystem folder to "pinctrl" since we will likely
want to keep other pin control such as biasing in this
subsystem too, so let us keep to something generic even though
we're mainly doing pinmux now.
- As a consequence, register pins as an abstract entity separate
from the pinmux. The muxing functions will claim pins out of the
pin pool and make sure they do not collide. Pins can now be
named by the pinctrl core.
- Converted the pin lookup from a static array into a radix tree,
I agreed with Grant Likely to try to avoid any static allocation
(which is crap for device tree stuff) so I just rewrote this
to be dynamic, just like irq number descriptors. The
platform-wide definition of number of pins goes away - this is
now just the sum total of the pins registered to the subsystem.
- Make sure mappings with only a function name and no device
works properly.

ChangeLog v3->v4:

- Define a number space per controller instead of globally,
Stephen and Grant requested the same thing so now maps need to
define target controller, and the radix tree of pin descriptors
is a property on each pin controller device.
- Add a compulsory pinctrl device entry to the pinctrl mapping
table. This must match the pinctrl device, like "pinctrl.0"
- Split the file core.c in two: core.c and pinmux.c where the
latter carry all pinmux stuff, the core is for generic pin
control, and use local headers to access functionality between
files. It is now possible to implement a "blank" pin controller
without pinmux capabilities. This split will make new additions
like pindrive.c, pinbias.c etc possible for combined drivers
and chunks of functionality which is a GoodThing(TM).
- Rewrite the interaction with the GPIO subsystem - the pin
controller descriptor now handles this by defining an offset
into the GPIO numberspace for its handled pin range. This is
used to look up the apropriate pin controller for a GPIO pin.
Then that specific GPIO range is matched 1-1 for the target
controller instance.
- Fixed a number of review comments from Joe Perches.
- Broke out a header file pinctrl.h for the core pin handling
stuff that will be reused by other stuff than pinmux.
- Fixed some erroneous EXPORT() stuff.
- Remove mispatched U300 Kconfig and Makefile entries
- Fixed a number of review comments from Stephen Warren, not all
of them - still WIP. But I think the new mapping that will
specify which function goes to which pin mux controller address
50% of your concerns (else beat me up).

ChangeLog v4->v5:

- Defined a "position" for each function, so the pin controller now
tracks a function in a certain position, and the pinmux maps define
what position you want the function in. (Feedback from Stephen
Warren and Sascha Hauer).
- Since we now need to request a combined function+position from
the machine mapping table that connect mux settings to drivers,
it was extended with a position field and a name field. The
name field is now used if you e.g. need to switch between two
mux map settings at runtime.
- Switched from a class device to using struct bus_type for this
subsystem. Verified sysfs functionality: seems to work fine.
(Feedback from Arnd Bergmann and Greg Kroah-Hartman)
- Define a per pincontroller list of GPIO ranges from the GPIO
pin space that can be handled by the pin controller. These can
be added one by one at runtime. (Feedback from Barry Song)
- Expanded documentation of regulator_[get|enable|disable|put]
semantics.
- Fixed a number of review comments from Barry Song. (Thanks!)

ChangeLog v5->v6:

- Create an abstract pin group concept that can sort pins into
named and enumerated groups no matter what the use of these
groups may be, one possible usecase is a group of pins being
muxed in or so. The intention is however to also use these
groups for other pin control activities.
- Make it compulsory for pinmux functions to associate with
at least one group, so the abstract pin group concept is used
to define the groups of pins affected by a pinmux function.
The pinmux driver interface has been altered so as to enforce
a function to list applicable groups per function.
- Provide an optional .group entry in the pinmux machine map
so the map can select beteween different available groups
to be used with a certain function.
- Consequent changes all over the place so that e.g. debugfs
present reasonable information about the world.
- Drop the per-pin mux (*config) function in the pinmux_ops
struct - I was afraid that this would start to be used for
things totally unrelated to muxing, we can introduce that to
the generic struct pinctrl_ops if needed. I want to keep
muxing orthogonal to other pin control subjects and not mix
these things up.

ChangeLog v6->v7:

- Make it possible to have several map entries matching the
same device, pin controller and function, but using
a different group, and alter the semantics so that
pinmux_get() will pick all matching map entries, and
store the associated groups in a list. The list will
then be iterated over at pinmux_enable()/pinmux_disable()
and corresponding driver functions called for each
defined group. Notice that you're only allowed to map
multiple *groups* to the same
{ device, pin controller, function } triplet, attempts
to map the same device to multiple pin controllers will
for example fail. This is hopefully the crucial feature
requested by Stephen Warren.
- Add a pinmux hogging field to the pinmux mapping entries,
and enable the pinmux core to hog pinmux map entries.
This currently only works for pinmuxes without assigned
devices as it looks now, but with device trees we can
look up the corresponding struct device * entries when
we register the pinmux driver, and have it hog each
pinmux map in turn, for a simple approach to
non-dynamic pin muxing. This addresses an issue from
Grant Likely that the machine should take care of as
much of the pinmux setup as possible, not the devices.
By supplying a list of hogs, it can now instruct the
core to take care of any static mappings.
- Switch pinmux group retrieveal function to grab an
array of strings representing the groups rather than an
array of unsigned and rewrite accordingly.
- Alter debugfs to show the grouplist handled by each
pinmux. Also add a list of hogs.
- Dynamically allocate a struct pinmux at pinmux_get() and
free it at pinmux_put(), then add these to the global
list of pinmuxes active as we go along.
- Go over the list of pinmux maps at pinmux_get() time
and repeatedly apply matches.
- Retrieve applicable groups per function from the driver
as a string array rather than a unsigned array, then
lookup the enumerators.
- Make the device to pinmux map a singleton - only allow the
mapping table to be registered once and even tag the
registration function with __init so it surely won't be
abused.
- Create a separate debugfs file to view the pinmux map at
runtime.
- Introduce a spin lock to the pin descriptor struct, lock it
when modifying pin status entries. Reported by Stijn Devriendt.
- Fix up the documentation after review from Stephen Warren.
- Let the GPIO ranges give names as const char * instead of some
fixed-length string.
- add a function to unregister GPIO ranges to mirror the
registration function.
- Privatized the struct pinctrl_device and removed it from the
<linux/pinctrl/pinctrl.h> API, the drivers do not need to know
the members of this struct. It is now in the local header
"core.h".
- Rename the concept of "anonymous" mux maps to "system" muxes
and add convenience macros and documentation.

ChangeLog v7->v8:

- Delete the leftover pinmux_config() function from the
<linux/pinctrl/pinmux.h> header.
- Fix a race condition found by Stijn Devriendt in pin_request()

ChangeLog v8->v9:

- Drop the bus_type and the sysfs attributes and all, we're not on
the clear about how this should be used for e.g. userspace
interfaces so let us save this for the future.
- Use the right name in MAINTAINERS, PIN CONTROL rather than
PINMUX
- Don't kfree() the device state holder, let the .remove() callback
handle this.
- Fix up numerous kerneldoc headers to have one line for the function
description and more verbose documentation below the parameters

ChangeLog v9->v10:
- pinctrl: EXPORT_SYMBOL needs export.h, folded in a patch
from Steven Rothwell
- fix pinctrl_register error handling, folded in a patch from
Axel Lin
- Various fixes to documentation text so that it's consistent.
- Removed pointless comment from drivers/Kconfig
- Removed dependency on SYSFS since we removed the bus in
v9.
- Renamed hopelessly abbreviated pctldev_* functions to the
more verbose pinctrl_dev_*
- Drop mutex properly when looking up GPIO ranges
- Return NULL instead of ERR_PTR() errors on registration of
pin controllers, using cast pointers is fragile. We can
live without the detailed error codes for sure.

Cc: Stijn Devriendt <highguy@gmail.com>
Cc: Joe Perches <joe@perches.com>
Cc: Russell King <linux@arm.linux.org.uk>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Barry Song <21cnbao@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>