Lines Matching defs:__SYSREG
30 #define __SYSREG(ADDR, TYPE) (*(volatile TYPE *)(ADDR))
33 #define __SYSREG(ADDR, TYPE) ADDR
88 #define CPUP __SYSREG(0xc0000020, u16) /* CPU pipeline register */
95 #define CPUM __SYSREG(0xc0000040, u16) /* CPU mode register */
122 #define DCR __SYSREG(0xc0000030, u16) /* Debug control register */
125 #define IVAR0 __SYSREG(0xc0000000, u16) /* interrupt vector 0 */
126 #define IVAR1 __SYSREG(0xc0000004, u16) /* interrupt vector 1 */
127 #define IVAR2 __SYSREG(0xc0000008, u16) /* interrupt vector 2 */
128 #define IVAR3 __SYSREG(0xc000000c, u16) /* interrupt vector 3 */
129 #define IVAR4 __SYSREG(0xc0000010, u16) /* interrupt vector 4 */
130 #define IVAR5 __SYSREG(0xc0000014, u16) /* interrupt vector 5 */
131 #define IVAR6 __SYSREG(0xc0000018, u16) /* interrupt vector 6 */
133 #define TBR __SYSREG(0xc0000024, u32) /* Trap table base */
137 #define DEAR __SYSREG(0xc0000038, u32) /* Data access exception address */
139 #define sISR __SYSREG(0xc0000044, u32) /* Supervisor interrupt status */
172 #define CHCTR __SYSREG(0xc0000070, u16) /* cache control */
187 #define ICIVCR __SYSREG(0xc0000c00, u32) /* icache area invalidate control */
191 #define ICIVMR __SYSREG(0xc0000c04, u32) /* icache area invalidate mask */
193 #define DCPGCR __SYSREG(0xc0000c10, u32) /* data cache area purge control */
198 #define DCPGMR __SYSREG(0xc0000c14, u32) /* data cache area purge mask */
202 #define MMUCTR __SYSREG(0xc0000090, u32) /* MMU control register */
228 #define PIDR __SYSREG(0xc0000094, u16) /* PID register */
231 #define PTBR __SYSREG(0xc0000098, unsigned long) /* Page table base register */
233 #define IPTEL __SYSREG(0xc00000a0, u32) /* instruction TLB entry */
234 #define DPTEL __SYSREG(0xc00000b0, u32) /* data TLB entry */
255 #define IPTEU __SYSREG(0xc00000a4, u32) /* instruction TLB virtual addr */
256 #define DPTEU __SYSREG(0xc00000b4, u32) /* data TLB virtual addr */
260 #define IPTEL2 __SYSREG(0xc00000a8, u32) /* instruction TLB entry */
261 #define DPTEL2 __SYSREG(0xc00000b8, u32) /* data TLB entry */
312 #define AAR __SYSREG(0xc0000a00, u32) /* cacheable address */
313 #define AAR2 __SYSREG(0xc0000a04, u32) /* uncacheable address */
314 #define ADR __SYSREG(0xc0000a08, u32) /* data */
315 #define ASR __SYSREG(0xc0000a0c, u32) /* status */
316 #define AARU __SYSREG(0xd400aa00, u32) /* user address */
317 #define ADRU __SYSREG(0xd400aa08, u32) /* user data */
318 #define ASRU __SYSREG(0xd400aa0c, u32) /* user status */