1/* MN10300 Core system registers 2 * 3 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. 4 * Written by David Howells (dhowells@redhat.com) 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public Licence 8 * as published by the Free Software Foundation; either version 9 * 2 of the Licence, or (at your option) any later version. 10 */ 11#ifndef _ASM_CPU_REGS_H 12#define _ASM_CPU_REGS_H 13 14#ifndef __ASSEMBLY__ 15#include <linux/types.h> 16#endif 17 18/* we tell the compiler to pretend to be AM33 so that it doesn't try and use 19 * the FP regs, but tell the assembler that we're actually allowed AM33v2 20 * instructions */ 21#ifndef __ASSEMBLY__ 22asm(" .am33_2\n"); 23#else 24.am33_2 25#endif 26 27#ifdef __KERNEL__ 28 29#ifndef __ASSEMBLY__ 30#define __SYSREG(ADDR, TYPE) (*(volatile TYPE *)(ADDR)) 31#define __SYSREGC(ADDR, TYPE) (*(const volatile TYPE *)(ADDR)) 32#else 33#define __SYSREG(ADDR, TYPE) ADDR 34#define __SYSREGC(ADDR, TYPE) ADDR 35#endif 36 37/* CPU registers */ 38#define EPSW_FLAG_Z 0x00000001 /* zero flag */ 39#define EPSW_FLAG_N 0x00000002 /* negative flag */ 40#define EPSW_FLAG_C 0x00000004 /* carry flag */ 41#define EPSW_FLAG_V 0x00000008 /* overflow flag */ 42#define EPSW_IM 0x00000700 /* interrupt mode */ 43#define EPSW_IM_0 0x00000000 /* interrupt mode 0 */ 44#define EPSW_IM_1 0x00000100 /* interrupt mode 1 */ 45#define EPSW_IM_2 0x00000200 /* interrupt mode 2 */ 46#define EPSW_IM_3 0x00000300 /* interrupt mode 3 */ 47#define EPSW_IM_4 0x00000400 /* interrupt mode 4 */ 48#define EPSW_IM_5 0x00000500 /* interrupt mode 5 */ 49#define EPSW_IM_6 0x00000600 /* interrupt mode 6 */ 50#define EPSW_IM_7 0x00000700 /* interrupt mode 7 */ 51#define EPSW_IE 0x00000800 /* interrupt enable */ 52#define EPSW_S 0x00003000 /* software auxiliary bits */ 53#define EPSW_T 0x00008000 /* trace enable */ 54#define EPSW_nSL 0x00010000 /* not supervisor level */ 55#define EPSW_NMID 0x00020000 /* nonmaskable interrupt disable */ 56#define EPSW_nAR 0x00040000 /* register bank control */ 57#define EPSW_ML 0x00080000 /* monitor level */ 58#define EPSW_FE 0x00100000 /* FPU enable */ 59#define EPSW_IM_SHIFT 8 /* EPSW_IM_SHIFT determines the interrupt mode */ 60 61#define NUM2EPSW_IM(num) ((num) << EPSW_IM_SHIFT) 62 63/* FPU registers */ 64#define FPCR_EF_I 0x00000001 /* inexact result FPU exception flag */ 65#define FPCR_EF_U 0x00000002 /* underflow FPU exception flag */ 66#define FPCR_EF_O 0x00000004 /* overflow FPU exception flag */ 67#define FPCR_EF_Z 0x00000008 /* zero divide FPU exception flag */ 68#define FPCR_EF_V 0x00000010 /* invalid operand FPU exception flag */ 69#define FPCR_EE_I 0x00000020 /* inexact result FPU exception enable */ 70#define FPCR_EE_U 0x00000040 /* underflow FPU exception enable */ 71#define FPCR_EE_O 0x00000080 /* overflow FPU exception enable */ 72#define FPCR_EE_Z 0x00000100 /* zero divide FPU exception enable */ 73#define FPCR_EE_V 0x00000200 /* invalid operand FPU exception enable */ 74#define FPCR_EC_I 0x00000400 /* inexact result FPU exception cause */ 75#define FPCR_EC_U 0x00000800 /* underflow FPU exception cause */ 76#define FPCR_EC_O 0x00001000 /* overflow FPU exception cause */ 77#define FPCR_EC_Z 0x00002000 /* zero divide FPU exception cause */ 78#define FPCR_EC_V 0x00004000 /* invalid operand FPU exception cause */ 79#define FPCR_RM 0x00030000 /* rounding mode */ 80#define FPCR_RM_NEAREST 0x00000000 /* - round to nearest value */ 81#define FPCR_FCC_U 0x00040000 /* FPU unordered condition code */ 82#define FPCR_FCC_E 0x00080000 /* FPU equal condition code */ 83#define FPCR_FCC_G 0x00100000 /* FPU greater than condition code */ 84#define FPCR_FCC_L 0x00200000 /* FPU less than condition code */ 85#define FPCR_INIT 0x00000000 /* no exceptions, rounding to nearest */ 86 87/* CPU control registers */ 88#define CPUP __SYSREG(0xc0000020, u16) /* CPU pipeline register */ 89#define CPUP_DWBD 0x0020 /* write buffer disable flag */ 90#define CPUP_IPFD 0x0040 /* instruction prefetch disable flag */ 91#define CPUP_EXM 0x0080 /* exception operation mode */ 92#define CPUP_EXM_AM33V1 0x0000 /* - AM33 v1 exception mode */ 93#define CPUP_EXM_AM33V2 0x0080 /* - AM33 v2 exception mode */ 94 95#define CPUM __SYSREG(0xc0000040, u16) /* CPU mode register */ 96#define CPUM_SLEEP 0x0004 /* set to enter sleep state */ 97#define CPUM_HALT 0x0008 /* set to enter halt state */ 98#define CPUM_STOP 0x0010 /* set to enter stop state */ 99 100#define CPUREV __SYSREGC(0xc0000050, u32) /* CPU revision register */ 101#define CPUREV_TYPE 0x0000000f /* CPU type */ 102#define CPUREV_TYPE_S 0 103#define CPUREV_TYPE_AM33_1 0x00000000 /* - AM33-1 core, AM33/1.00 arch */ 104#define CPUREV_TYPE_AM33_2 0x00000001 /* - AM33-2 core, AM33/2.00 arch */ 105#define CPUREV_TYPE_AM34_1 0x00000002 /* - AM34-1 core, AM33/2.00 arch */ 106#define CPUREV_TYPE_AM33_3 0x00000003 /* - AM33-3 core, AM33/2.00 arch */ 107#define CPUREV_TYPE_AM34_2 0x00000004 /* - AM34-2 core, AM33/3.00 arch */ 108#define CPUREV_REVISION 0x000000f0 /* CPU revision */ 109#define CPUREV_REVISION_S 4 110#define CPUREV_ICWAY 0x00000f00 /* number of instruction cache ways */ 111#define CPUREV_ICWAY_S 8 112#define CPUREV_ICSIZE 0x0000f000 /* instruction cache way size */ 113#define CPUREV_ICSIZE_S 12 114#define CPUREV_DCWAY 0x000f0000 /* number of data cache ways */ 115#define CPUREV_DCWAY_S 16 116#define CPUREV_DCSIZE 0x00f00000 /* data cache way size */ 117#define CPUREV_DCSIZE_S 20 118#define CPUREV_FPUTYPE 0x0f000000 /* FPU core type */ 119#define CPUREV_FPUTYPE_NONE 0x00000000 /* - no FPU core implemented */ 120#define CPUREV_OCDCTG 0xf0000000 /* on-chip debug function category */ 121 122#define DCR __SYSREG(0xc0000030, u16) /* Debug control register */ 123 124/* interrupt/exception control registers */ 125#define IVAR0 __SYSREG(0xc0000000, u16) /* interrupt vector 0 */ 126#define IVAR1 __SYSREG(0xc0000004, u16) /* interrupt vector 1 */ 127#define IVAR2 __SYSREG(0xc0000008, u16) /* interrupt vector 2 */ 128#define IVAR3 __SYSREG(0xc000000c, u16) /* interrupt vector 3 */ 129#define IVAR4 __SYSREG(0xc0000010, u16) /* interrupt vector 4 */ 130#define IVAR5 __SYSREG(0xc0000014, u16) /* interrupt vector 5 */ 131#define IVAR6 __SYSREG(0xc0000018, u16) /* interrupt vector 6 */ 132 133#define TBR __SYSREG(0xc0000024, u32) /* Trap table base */ 134#define TBR_TB 0xff000000 /* table base address bits 31-24 */ 135#define TBR_INT_CODE 0x00ffffff /* interrupt code */ 136 137#define DEAR __SYSREG(0xc0000038, u32) /* Data access exception address */ 138 139#define sISR __SYSREG(0xc0000044, u32) /* Supervisor interrupt status */ 140#define sISR_IRQICE 0x00000001 /* ICE interrupt */ 141#define sISR_ISTEP 0x00000002 /* single step interrupt */ 142#define sISR_MISSA 0x00000004 /* memory access address misalignment fault */ 143#define sISR_UNIMP 0x00000008 /* unimplemented instruction execution fault */ 144#define sISR_PIEXE 0x00000010 /* program interrupt */ 145#define sISR_MEMERR 0x00000020 /* illegal memory access fault */ 146#define sISR_IBREAK 0x00000040 /* instraction break interrupt */ 147#define sISR_DBSRL 0x00000080 /* debug serial interrupt */ 148#define sISR_PERIDB 0x00000100 /* peripheral debug interrupt */ 149#define sISR_EXUNIMP 0x00000200 /* unimplemented ex-instruction execution fault */ 150#define sISR_OBREAK 0x00000400 /* operand break interrupt */ 151#define sISR_PRIV 0x00000800 /* privileged instruction execution fault */ 152#define sISR_BUSERR 0x00001000 /* bus error fault */ 153#define sISR_DBLFT 0x00002000 /* double fault */ 154#define sISR_DBG 0x00008000 /* debug reserved interrupt */ 155#define sISR_ITMISS 0x00010000 /* instruction TLB miss */ 156#define sISR_DTMISS 0x00020000 /* data TLB miss */ 157#define sISR_ITEX 0x00040000 /* instruction TLB access exception */ 158#define sISR_DTEX 0x00080000 /* data TLB access exception */ 159#define sISR_ILGIA 0x00100000 /* illegal instruction access exception */ 160#define sISR_ILGDA 0x00200000 /* illegal data access exception */ 161#define sISR_IOIA 0x00400000 /* internal I/O space instruction access excep */ 162#define sISR_PRIVA 0x00800000 /* privileged space instruction access excep */ 163#define sISR_PRIDA 0x01000000 /* privileged space data access excep */ 164#define sISR_DISA 0x02000000 /* data space instruction access excep */ 165#define sISR_SYSC 0x04000000 /* system call instruction excep */ 166#define sISR_FPUD 0x08000000 /* FPU disabled excep */ 167#define sISR_FPUUI 0x10000000 /* FPU unimplemented instruction excep */ 168#define sISR_FPUOP 0x20000000 /* FPU operation excep */ 169#define sISR_NE 0x80000000 /* multiple synchronous exceptions excep */ 170 171/* cache control registers */ 172#define CHCTR __SYSREG(0xc0000070, u16) /* cache control */ 173#define CHCTR_ICEN 0x0001 /* instruction cache enable */ 174#define CHCTR_DCEN 0x0002 /* data cache enable */ 175#define CHCTR_ICBUSY 0x0004 /* instruction cache busy */ 176#define CHCTR_DCBUSY 0x0008 /* data cache busy */ 177#define CHCTR_ICINV 0x0010 /* instruction cache invalidate */ 178#define CHCTR_DCINV 0x0020 /* data cache invalidate */ 179#define CHCTR_DCWTMD 0x0040 /* data cache writing mode */ 180#define CHCTR_DCWTMD_WRBACK 0x0000 /* - write back mode */ 181#define CHCTR_DCWTMD_WRTHROUGH 0x0040 /* - write through mode */ 182#define CHCTR_DCALMD 0x0080 /* data cache allocation mode */ 183#define CHCTR_ICWMD 0x0f00 /* instruction cache way mode */ 184#define CHCTR_DCWMD 0xf000 /* data cache way mode */ 185 186#ifdef CONFIG_AM34_2 187#define ICIVCR __SYSREG(0xc0000c00, u32) /* icache area invalidate control */ 188#define ICIVCR_ICIVBSY 0x00000008 /* icache area invalidate busy */ 189#define ICIVCR_ICI 0x00000001 /* icache area invalidate */ 190 191#define ICIVMR __SYSREG(0xc0000c04, u32) /* icache area invalidate mask */ 192 193#define DCPGCR __SYSREG(0xc0000c10, u32) /* data cache area purge control */ 194#define DCPGCR_DCPGBSY 0x00000008 /* data cache area purge busy */ 195#define DCPGCR_DCP 0x00000002 /* data cache area purge */ 196#define DCPGCR_DCI 0x00000001 /* data cache area invalidate */ 197 198#define DCPGMR __SYSREG(0xc0000c14, u32) /* data cache area purge mask */ 199#endif /* CONFIG_AM34_2 */ 200 201/* MMU control registers */ 202#define MMUCTR __SYSREG(0xc0000090, u32) /* MMU control register */ 203#define MMUCTR_IRP 0x0000003f /* instruction TLB replace pointer */ 204#define MMUCTR_ITE 0x00000040 /* instruction TLB enable */ 205#define MMUCTR_IIV 0x00000080 /* instruction TLB invalidate */ 206#define MMUCTR_ITL 0x00000700 /* instruction TLB lock pointer */ 207#define MMUCTR_ITL_NOLOCK 0x00000000 /* - no lock */ 208#define MMUCTR_ITL_LOCK0 0x00000100 /* - entry 0 locked */ 209#define MMUCTR_ITL_LOCK0_1 0x00000200 /* - entry 0-1 locked */ 210#define MMUCTR_ITL_LOCK0_3 0x00000300 /* - entry 0-3 locked */ 211#define MMUCTR_ITL_LOCK0_7 0x00000400 /* - entry 0-7 locked */ 212#define MMUCTR_ITL_LOCK0_15 0x00000500 /* - entry 0-15 locked */ 213#define MMUCTR_CE 0x00008000 /* cacheable bit enable */ 214#define MMUCTR_DRP 0x003f0000 /* data TLB replace pointer */ 215#define MMUCTR_DTE 0x00400000 /* data TLB enable */ 216#define MMUCTR_DIV 0x00800000 /* data TLB invalidate */ 217#define MMUCTR_DTL 0x07000000 /* data TLB lock pointer */ 218#define MMUCTR_DTL_NOLOCK 0x00000000 /* - no lock */ 219#define MMUCTR_DTL_LOCK0 0x01000000 /* - entry 0 locked */ 220#define MMUCTR_DTL_LOCK0_1 0x02000000 /* - entry 0-1 locked */ 221#define MMUCTR_DTL_LOCK0_3 0x03000000 /* - entry 0-3 locked */ 222#define MMUCTR_DTL_LOCK0_7 0x04000000 /* - entry 0-7 locked */ 223#define MMUCTR_DTL_LOCK0_15 0x05000000 /* - entry 0-15 locked */ 224#ifdef CONFIG_AM34_2 225#define MMUCTR_WTE 0x80000000 /* write-through cache TLB entry bit enable */ 226#endif 227 228#define PIDR __SYSREG(0xc0000094, u16) /* PID register */ 229#define PIDR_PID 0x00ff /* process identifier */ 230 231#define PTBR __SYSREG(0xc0000098, unsigned long) /* Page table base register */ 232 233#define IPTEL __SYSREG(0xc00000a0, u32) /* instruction TLB entry */ 234#define DPTEL __SYSREG(0xc00000b0, u32) /* data TLB entry */ 235#define xPTEL_V 0x00000001 /* TLB entry valid */ 236#define xPTEL_UNUSED1 0x00000002 /* unused bit */ 237#define xPTEL_UNUSED2 0x00000004 /* unused bit */ 238#define xPTEL_C 0x00000008 /* cached if set */ 239#define xPTEL_PV 0x00000010 /* page valid */ 240#define xPTEL_D 0x00000020 /* dirty */ 241#define xPTEL_PR 0x000001c0 /* page protection */ 242#define xPTEL_PR_ROK 0x00000000 /* - R/O kernel */ 243#define xPTEL_PR_RWK 0x00000100 /* - R/W kernel */ 244#define xPTEL_PR_ROK_ROU 0x00000080 /* - R/O kernel and R/O user */ 245#define xPTEL_PR_RWK_ROU 0x00000180 /* - R/W kernel and R/O user */ 246#define xPTEL_PR_RWK_RWU 0x000001c0 /* - R/W kernel and R/W user */ 247#define xPTEL_G 0x00000200 /* global (use PID if 0) */ 248#define xPTEL_PS 0x00000c00 /* page size */ 249#define xPTEL_PS_4Kb 0x00000000 /* - 4Kb page */ 250#define xPTEL_PS_128Kb 0x00000400 /* - 128Kb page */ 251#define xPTEL_PS_1Kb 0x00000800 /* - 1Kb page */ 252#define xPTEL_PS_4Mb 0x00000c00 /* - 4Mb page */ 253#define xPTEL_PPN 0xfffff006 /* physical page number */ 254 255#define IPTEU __SYSREG(0xc00000a4, u32) /* instruction TLB virtual addr */ 256#define DPTEU __SYSREG(0xc00000b4, u32) /* data TLB virtual addr */ 257#define xPTEU_VPN 0xfffffc00 /* virtual page number */ 258#define xPTEU_PID 0x000000ff /* process identifier to which applicable */ 259 260#define IPTEL2 __SYSREG(0xc00000a8, u32) /* instruction TLB entry */ 261#define DPTEL2 __SYSREG(0xc00000b8, u32) /* data TLB entry */ 262#define xPTEL2_V 0x00000001 /* TLB entry valid */ 263#define xPTEL2_C 0x00000002 /* cacheable */ 264#define xPTEL2_PV 0x00000004 /* page valid */ 265#define xPTEL2_D 0x00000008 /* dirty */ 266#define xPTEL2_PR 0x00000070 /* page protection */ 267#define xPTEL2_PR_ROK 0x00000000 /* - R/O kernel */ 268#define xPTEL2_PR_RWK 0x00000040 /* - R/W kernel */ 269#define xPTEL2_PR_ROK_ROU 0x00000020 /* - R/O kernel and R/O user */ 270#define xPTEL2_PR_RWK_ROU 0x00000060 /* - R/W kernel and R/O user */ 271#define xPTEL2_PR_RWK_RWU 0x00000070 /* - R/W kernel and R/W user */ 272#define xPTEL2_G 0x00000080 /* global (use PID if 0) */ 273#define xPTEL2_PS 0x00000300 /* page size */ 274#define xPTEL2_PS_4Kb 0x00000000 /* - 4Kb page */ 275#define xPTEL2_PS_128Kb 0x00000100 /* - 128Kb page */ 276#define xPTEL2_PS_1Kb 0x00000200 /* - 1Kb page */ 277#define xPTEL2_PS_4Mb 0x00000300 /* - 4Mb page */ 278#define xPTEL2_CWT 0x00000400 /* cacheable write-through */ 279#define xPTEL2_UNUSED1 0x00000800 /* unused bit (broadcast mask) */ 280#define xPTEL2_PPN 0xfffff000 /* physical page number */ 281 282#define xPTEL2_V_BIT 0 /* bit numbers corresponding to above masks */ 283#define xPTEL2_C_BIT 1 284#define xPTEL2_PV_BIT 2 285#define xPTEL2_D_BIT 3 286#define xPTEL2_G_BIT 7 287#define xPTEL2_UNUSED1_BIT 11 288 289#define MMUFCR __SYSREGC(0xc000009c, u32) /* MMU exception cause */ 290#define MMUFCR_IFC __SYSREGC(0xc000009c, u16) /* MMU instruction excep cause */ 291#define MMUFCR_DFC __SYSREGC(0xc000009e, u16) /* MMU data exception cause */ 292#define MMUFCR_xFC_TLBMISS 0x0001 /* TLB miss flag */ 293#define MMUFCR_xFC_INITWR 0x0002 /* initial write excep flag */ 294#define MMUFCR_xFC_PGINVAL 0x0004 /* page invalid excep flag */ 295#define MMUFCR_xFC_PROTVIOL 0x0008 /* protection violation excep flag */ 296#define MMUFCR_xFC_ACCESS 0x0010 /* access level flag */ 297#define MMUFCR_xFC_ACCESS_USR 0x0000 /* - user mode */ 298#define MMUFCR_xFC_ACCESS_SR 0x0010 /* - supervisor mode */ 299#define MMUFCR_xFC_TYPE 0x0020 /* access type flag */ 300#define MMUFCR_xFC_TYPE_READ 0x0000 /* - read */ 301#define MMUFCR_xFC_TYPE_WRITE 0x0020 /* - write */ 302#define MMUFCR_xFC_PR 0x01c0 /* page protection flag */ 303#define MMUFCR_xFC_PR_ROK 0x0000 /* - R/O kernel */ 304#define MMUFCR_xFC_PR_RWK 0x0100 /* - R/W kernel */ 305#define MMUFCR_xFC_PR_ROK_ROU 0x0080 /* - R/O kernel and R/O user */ 306#define MMUFCR_xFC_PR_RWK_ROU 0x0180 /* - R/W kernel and R/O user */ 307#define MMUFCR_xFC_PR_RWK_RWU 0x01c0 /* - R/W kernel and R/W user */ 308#define MMUFCR_xFC_ILLADDR 0x0200 /* illegal address excep flag */ 309 310#ifdef CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT 311/* atomic operation registers */ 312#define AAR __SYSREG(0xc0000a00, u32) /* cacheable address */ 313#define AAR2 __SYSREG(0xc0000a04, u32) /* uncacheable address */ 314#define ADR __SYSREG(0xc0000a08, u32) /* data */ 315#define ASR __SYSREG(0xc0000a0c, u32) /* status */ 316#define AARU __SYSREG(0xd400aa00, u32) /* user address */ 317#define ADRU __SYSREG(0xd400aa08, u32) /* user data */ 318#define ASRU __SYSREG(0xd400aa0c, u32) /* user status */ 319 320#define ASR_RW 0x00000008 /* read */ 321#define ASR_BW 0x00000004 /* bus error */ 322#define ASR_IW 0x00000002 /* interrupt */ 323#define ASR_LW 0x00000001 /* bus lock */ 324 325#define ASRU_RW ASR_RW /* read */ 326#define ASRU_BW ASR_BW /* bus error */ 327#define ASRU_IW ASR_IW /* interrupt */ 328#define ASRU_LW ASR_LW /* bus lock */ 329 330/* in inline ASM, we stick the base pointer in to a reg and use offsets from 331 * it */ 332#define ATOMIC_OPS_BASE_ADDR 0xc0000a00 333#ifndef __ASSEMBLY__ 334asm( 335 "_AAR = 0\n" 336 "_AAR2 = 4\n" 337 "_ADR = 8\n" 338 "_ASR = 12\n"); 339#else 340#define _AAR 0 341#define _AAR2 4 342#define _ADR 8 343#define _ASR 12 344#endif 345 346/* physical page address for userspace atomic operations registers */ 347#define USER_ATOMIC_OPS_PAGE_ADDR 0xd400a000 348 349#endif /* CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT */ 350 351#endif /* __KERNEL__ */ 352 353#endif /* _ASM_CPU_REGS_H */ 354