Lines Matching refs:pipe
28 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
32 #define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \
33 (pipe) == PIPE_B ? (b) : (c))
475 #define GEN7_PIPE_DE_LOAD_SL(pipe) _PIPE(pipe, \
522 #define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
523 #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
524 #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
525 #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
526 #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
527 #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
528 #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
529 #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
530 #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
531 #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
532 #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
533 #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
674 * Generally the common lane corresponds to the pipe and
679 * pipe A == CMN/PLL/REF CH0
681 * pipe B == CMN/PLL/REF CH1
688 * ie. drive port B with pipe B, or port C with pipe A.
692 * pipe C == CMN/PLL/REF CH0
732 #define DPIO_PHY(pipe) ((pipe) >> 1)
736 * Per pipe/PLL DPIO regs
1182 #define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + pipe*3))
1184 #define ERR_INT_FIFO_UNDERRUN(pipe) (1<<(pipe*3))
1684 #define DPLL(pipe) _PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
1772 #define DPLL_MD(pipe) _PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
1815 #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
1816 #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
1972 #define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \
2377 /* with DP port the pipe source is invalid */
2385 /* with DP/TV port the pipe source is invalid */
2413 #define PIPE_CRC_CTL(pipe) _TRANSCODER2(pipe, _PIPE_CRC_CTL_A)
2414 #define PIPE_CRC_RES_1_IVB(pipe) \
2415 _TRANSCODER2(pipe, _PIPE_CRC_RES_1_A_IVB)
2416 #define PIPE_CRC_RES_2_IVB(pipe) \
2417 _TRANSCODER2(pipe, _PIPE_CRC_RES_2_A_IVB)
2418 #define PIPE_CRC_RES_3_IVB(pipe) \
2419 _TRANSCODER2(pipe, _PIPE_CRC_RES_3_A_IVB)
2420 #define PIPE_CRC_RES_4_IVB(pipe) \
2421 _TRANSCODER2(pipe, _PIPE_CRC_RES_4_A_IVB)
2422 #define PIPE_CRC_RES_5_IVB(pipe) \
2423 _TRANSCODER2(pipe, _PIPE_CRC_RES_5_A_IVB)
2425 #define PIPE_CRC_RES_RED(pipe) \
2426 _TRANSCODER2(pipe, _PIPE_CRC_RES_RED_A)
2427 #define PIPE_CRC_RES_GREEN(pipe) \
2428 _TRANSCODER2(pipe, _PIPE_CRC_RES_GREEN_A)
2429 #define PIPE_CRC_RES_BLUE(pipe) \
2430 _TRANSCODER2(pipe, _PIPE_CRC_RES_BLUE_A)
2431 #define PIPE_CRC_RES_RES1_I915(pipe) \
2432 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES1_A_I915)
2433 #define PIPE_CRC_RES_RES2_G4X(pipe) \
2434 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
2466 #define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \
2558 #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
2712 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
2754 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
2758 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
2800 * the DPLL semantics change when the LVDS is assigned to that pipe.
2803 /* Selects pipe B for LVDS data. Must be set on pre-965. */
2806 #define LVDS_PIPE(pipe) ((pipe) << 30)
2886 * - pipe enabled
2947 #define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
2952 #define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
2957 #define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
2973 #define BLM_PIPE(pipe) ((pipe) << 29)
3033 /* Sources the TV encoder input from pipe B instead of A. */
3115 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
3518 #define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16)
3696 #define PIPE_DATA_M_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
3697 #define PIPE_DATA_N_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
3698 #define PIPE_LINK_M_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
3699 #define PIPE_LINK_N_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
3712 #define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */
3807 * There's actually no pipe EDP. Some pipe registers have
3808 * simply shifted from the pipe to the transcoder, while
3814 #define _PIPE2(pipe, reg) (dev_priv->info.pipe_offsets[pipe] - \
3818 #define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF)
3819 #define PIPEDSL(pipe) _PIPE2(pipe, _PIPEADSL)
3820 #define PIPEFRAME(pipe) _PIPE2(pipe, _PIPEAFRAMEHIGH)
3821 #define PIPEFRAMEPIXEL(pipe) _PIPE2(pipe, _PIPEAFRAMEPIXEL)
3822 #define PIPESTAT(pipe) _PIPE2(pipe, _PIPEASTAT)
3834 #define PIPEMISC(pipe) _PIPE2(pipe, _PIPE_MISC_A)
4029 #define VLV_DDL(pipe) (VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
4124 * The two pipe frame counter registers are not synchronized, so
4149 #define PIPE_FRMCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_GM45)
4150 #define PIPE_FLIPCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_GM45)
4196 #define _CURSOR2(pipe, reg) (dev_priv->info.cursor_offsets[(pipe)] - \
4200 #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
4201 #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
4202 #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
4366 #define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
4367 #define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
4368 #define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
4369 #define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
4370 #define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
4371 #define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
4372 #define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
4373 #define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
4374 #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
4375 #define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
4376 #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
4377 #define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
4440 #define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
4441 #define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
4442 #define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
4443 #define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)
4444 #define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
4445 #define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
4446 #define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
4447 #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
4448 #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
4449 #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
4450 #define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
4451 #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
4452 #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
4453 #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
4500 #define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
4501 #define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
4502 #define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
4503 #define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
4504 #define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
4505 #define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL)
4506 #define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
4507 #define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
4508 #define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
4509 #define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
4510 #define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
4511 #define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)
4607 #define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29)
4622 #define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
4623 #define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
4624 #define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
4625 #define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
4626 #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
4631 #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
4635 #define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
4665 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe)))
4671 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe)))
4673 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe)))
4691 #define DE_PIPE_VBLANK_IVB(pipe) (1 << (pipe * 5))
4715 #define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+pipe))
4734 #define GEN8_DE_PIPE_ISR(pipe) (0x44400 + (0x10 * (pipe)))
4735 #define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe)))
4736 #define GEN8_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe)))
4737 #define GEN8_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe)))
4805 #define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
4944 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<(pipe*3))
5043 #define TRANS_DPLLB_SEL(pipe) (1 << (pipe * 4))
5044 #define TRANS_DPLLA_SEL(pipe) 0
5045 #define TRANS_DPLL_ENABLE(pipe) (1 << (pipe * 4 + 3))
5087 #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
5088 #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
5089 #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
5104 #define VLV_TVIDEO_DIP_CTL(pipe) \
5105 _PIPE3((pipe), VLV_VIDEO_DIP_CTL_A, \
5107 #define VLV_TVIDEO_DIP_DATA(pipe) \
5108 _PIPE3((pipe), VLV_VIDEO_DIP_DATA_A, \
5110 #define VLV_TVIDEO_DIP_GCP(pipe) \
5111 _PIPE3((pipe), VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
5169 #define PCH_TRANS_HTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
5170 #define PCH_TRANS_HBLANK(pipe) _PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
5171 #define PCH_TRANS_HSYNC(pipe) _PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
5172 #define PCH_TRANS_VTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
5173 #define PCH_TRANS_VBLANK(pipe) _PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
5174 #define PCH_TRANS_VSYNC(pipe) _PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
5175 #define PCH_TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, \
5187 #define PCH_TRANS_DATA_M1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
5188 #define PCH_TRANS_DATA_N1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
5189 #define PCH_TRANS_DATA_M2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
5190 #define PCH_TRANS_DATA_N2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
5191 #define PCH_TRANS_LINK_M1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
5192 #define PCH_TRANS_LINK_N1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
5193 #define PCH_TRANS_LINK_M2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
5194 #define PCH_TRANS_LINK_N2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
5198 #define PCH_TRANSCONF(pipe) _PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
5220 #define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
5224 #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
5234 #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
5235 #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
5246 #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
5257 #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
5307 #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
5343 #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
5349 #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
5350 #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
5369 #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
5370 #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
5392 #define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
5393 #define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
5394 #define VLV_PIPE_PP_ON_DELAYS(pipe) \
5395 _PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
5396 #define VLV_PIPE_PP_OFF_DELAYS(pipe) \
5397 _PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
5398 #define VLV_PIPE_PP_DIVISOR(pipe) \
5399 _PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
5462 #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
5471 #define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)
5783 #define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
5788 #define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
5800 #define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
5805 #define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
5812 #define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
5817 #define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \
5830 #define IBX_AUD_CFG(pipe) _PIPE(pipe, \
5835 #define CPT_AUD_CFG(pipe) _PIPE(pipe, \
5840 #define VLV_AUD_CFG(pipe) _PIPE(pipe, \
5867 #define HSW_AUD_CFG(pipe) _PIPE(pipe, \
5873 #define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \
5879 #define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
5886 #define AUD_DIG_CNVT(pipe) _PIPE(pipe, \
5893 #define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
5897 #define HSW_AUD_PIPE_CONV_CFG 0x6507c /* Audio pipe and converter configs */
5925 /* Per-pipe DDI Function Control */
5933 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
6139 #define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \
6162 /* pipe CSC */
6194 #define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
6195 #define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
6196 #define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
6197 #define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
6198 #define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
6199 #define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
6200 #define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
6201 #define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
6202 #define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
6203 #define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
6204 #define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
6205 #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
6206 #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
6593 /* XXX: only pipe A ?!? */