Lines Matching refs:pipe
109 int pipe = intel_crtc->pipe;
123 I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
126 val = I915_READ(MIPI_PORT_CTRL(pipe));
127 I915_WRITE(MIPI_PORT_CTRL(pipe), val | LP_OUTPUT_HOLD);
130 I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT);
133 I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY);
143 int pipe = intel_crtc->pipe;
149 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4);
161 temp = I915_READ(MIPI_PORT_CTRL(pipe)) & ~LANE_CONFIGURATION_MASK;
163 I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE);
164 POSTING_READ(MIPI_PORT_CTRL(pipe));
174 enum pipe pipe = intel_crtc->pipe;
179 /* Disable DPOunit clock gating, can stall pipe
181 tmp = I915_READ(DPLL(pipe));
183 I915_WRITE(DPLL(pipe), tmp);
207 * recommendation, port should be enabled befor plane & pipe */
215 /* for DSI port enable has to be done before pipe
240 int pipe = intel_crtc->pipe;
249 temp = I915_READ(MIPI_PORT_CTRL(pipe));
250 I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE);
251 POSTING_READ(MIPI_PORT_CTRL(pipe));
257 I915_WRITE(MIPI_DEVICE_READY(pipe), 0x0);
259 temp = I915_READ(MIPI_CTRL(pipe));
261 I915_WRITE(MIPI_CTRL(pipe), temp |
265 I915_WRITE(MIPI_EOT_DISABLE(pipe), CLOCKSTOP);
267 temp = I915_READ(MIPI_DSI_FUNC_PRG(pipe));
269 I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), temp);
271 I915_WRITE(MIPI_DEVICE_READY(pipe), 0x1);
285 int pipe = intel_crtc->pipe;
290 I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER);
293 I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT);
296 I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER);
299 if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & AFE_LATCHOUT)
303 val = I915_READ(MIPI_PORT_CTRL(pipe));
304 I915_WRITE(MIPI_PORT_CTRL(pipe), val & ~LP_OUTPUT_HOLD);
307 I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00);
337 enum pipe *pipe)
342 enum pipe p;
357 *pipe = p;
440 int pipe = intel_crtc->pipe;
463 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive);
464 I915_WRITE(MIPI_HFP_COUNT(pipe), hfp);
468 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(pipe), hsync);
469 I915_WRITE(MIPI_HBP_COUNT(pipe), hbp);
472 I915_WRITE(MIPI_VFP_COUNT(pipe), vfp);
473 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(pipe), vsync);
474 I915_WRITE(MIPI_VBP_COUNT(pipe), vbp);
486 int pipe = intel_crtc->pipe;
490 DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe));
498 /* read request priority is per pipe */
499 tmp = I915_READ(MIPI_CTRL(pipe));
501 I915_WRITE(MIPI_CTRL(pipe), tmp | READ_REQUEST_PRIORITY_HIGH);
504 I915_WRITE(MIPI_INTR_STAT(pipe), 0xffffffff);
505 I915_WRITE(MIPI_INTR_EN(pipe), 0xffffffff);
507 I915_WRITE(MIPI_DPHY_PARAM(pipe), intel_dsi->dphy_reg);
509 I915_WRITE(MIPI_DPI_RESOLUTION(pipe),
525 I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val);
546 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
551 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
557 I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), intel_dsi->lp_rx_timeout);
558 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), intel_dsi->turn_arnd_val);
559 I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), intel_dsi->rst_timer_val);
564 I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(intel_dsi->escape_clk_div, 100));
574 I915_WRITE(MIPI_EOT_DISABLE(pipe), val);
577 I915_WRITE(MIPI_INIT_COUNT(pipe), intel_dsi->init_count);
584 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe),
592 I915_WRITE(MIPI_LP_BYTECLK(pipe), intel_dsi->lp_byte_clk);
599 I915_WRITE(MIPI_DBI_BW_CTRL(pipe), intel_dsi->bw_timer);
601 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe),
609 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe),