Lines Matching refs:lp
61 #define SMC_IO_SHIFT (lp->io_shift)
272 #define SMC_IO_SHIFT (lp->io_shift)
360 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
362 smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
365 u_long physaddr = lp->physaddr;
382 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
392 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
399 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
401 smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
404 u_long physaddr = lp->physaddr;
421 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
431 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
537 #define TCR_REG(lp) SMC_REG(lp, 0x0000, 0)
556 #define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0)
575 #define RCR_REG(lp) SMC_REG(lp, 0x0004, 0)
592 #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
597 #define MIR_REG(lp) SMC_REG(lp, 0x0008, 0)
602 #define RPC_REG(lp) SMC_REG(lp, 0x000A, 0)
628 #define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1)
640 #define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
645 #define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1)
646 #define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1)
647 #define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1)
652 #define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
657 #define CTL_REG(lp) SMC_REG(lp, 0x000C, 1)
670 #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
684 #define PN_REG(lp) SMC_REG(lp, 0x0002, 2)
689 #define AR_REG(lp) SMC_REG(lp, 0x0003, 2)
695 #define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
700 #define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2)
703 #define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
707 #define PTR_REG(lp) SMC_REG(lp, 0x0006, 2)
715 #define DATA_REG(lp) SMC_REG(lp, 0x0008, 2)
720 #define INT_REG(lp) SMC_REG(lp, 0x000C, 2)
725 #define IM_REG(lp) SMC_REG(lp, 0x000D, 2)
738 #define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3)
739 #define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3)
740 #define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3)
741 #define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3)
746 #define MII_REG(lp) SMC_REG(lp, 0x0008, 3)
757 #define REV_REG(lp) SMC_REG(lp, 0x000A, 3)
763 #define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3)
770 #define EXT_REG(lp) SMC_REG(lp, 0x0000, 7)
894 #define SMC_REG(lp, reg, bank) \
896 int __b = SMC_CURRENT_BANK(lp); \
905 #define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT)
917 #define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp)
919 #define SMC_GET_PN(lp) \
920 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \
921 : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
923 #define SMC_SET_PN(lp, x) \
925 if (SMC_MUST_ALIGN_WRITE(lp)) \
926 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
927 else if (SMC_8BIT(lp)) \
928 SMC_outb(x, ioaddr, PN_REG(lp)); \
930 SMC_outw(x, ioaddr, PN_REG(lp)); \
933 #define SMC_GET_AR(lp) \
934 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \
935 : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
937 #define SMC_GET_TXFIFO(lp) \
938 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \
939 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
941 #define SMC_GET_RXFIFO(lp) \
942 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \
943 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
945 #define SMC_GET_INT(lp) \
946 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \
947 : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
949 #define SMC_ACK_INT(lp, x) \
951 if (SMC_8BIT(lp)) \
952 SMC_outb(x, ioaddr, INT_REG(lp)); \
957 __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
958 SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \
963 #define SMC_GET_INT_MASK(lp) \
964 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \
965 : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
967 #define SMC_SET_INT_MASK(lp, x) \
969 if (SMC_8BIT(lp)) \
970 SMC_outb(x, ioaddr, IM_REG(lp)); \
972 SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \
975 #define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT)
977 #define SMC_SELECT_BANK(lp, x) \
979 if (SMC_MUST_ALIGN_WRITE(lp)) \
985 #define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp))
987 #define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp))
989 #define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp))
991 #define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp))
993 #define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp))
995 #define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp))
997 #define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp))
999 #define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp))
1001 #define SMC_GET_GP(lp) SMC_inw(ioaddr, GP_REG(lp))
1003 #define SMC_SET_GP(lp, x) \
1005 if (SMC_MUST_ALIGN_WRITE(lp)) \
1006 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1)); \
1008 SMC_outw(x, ioaddr, GP_REG(lp)); \
1011 #define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp))
1013 #define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp))
1015 #define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp))
1017 #define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp))
1019 #define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp))
1021 #define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp))
1023 #define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp))
1025 #define SMC_SET_PTR(lp, x) \
1027 if (SMC_MUST_ALIGN_WRITE(lp)) \
1028 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
1030 SMC_outw(x, ioaddr, PTR_REG(lp)); \
1033 #define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp))
1035 #define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp))
1037 #define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp))
1039 #define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp))
1041 #define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp))
1043 #define SMC_SET_RPC(lp, x) \
1045 if (SMC_MUST_ALIGN_WRITE(lp)) \
1046 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \
1048 SMC_outw(x, ioaddr, RPC_REG(lp)); \
1051 #define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp))
1053 #define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp))
1056 #define SMC_GET_MAC_ADDR(lp, addr) \
1059 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
1061 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
1063 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
1068 #define SMC_SET_MAC_ADDR(lp, addr) \
1070 SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1071 SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1072 SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1075 #define SMC_SET_MCAST(lp, x) \
1078 SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1079 SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1080 SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1081 SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1084 #define SMC_PUT_PKT_HDR(lp, status, length) \
1086 if (SMC_32BIT(lp)) \
1088 DATA_REG(lp)); \
1090 SMC_outw(status, ioaddr, DATA_REG(lp)); \
1091 SMC_outw(length, ioaddr, DATA_REG(lp)); \
1095 #define SMC_GET_PKT_HDR(lp, status, length) \
1097 if (SMC_32BIT(lp)) { \
1098 unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
1102 (status) = SMC_inw(ioaddr, DATA_REG(lp)); \
1103 (length) = SMC_inw(ioaddr, DATA_REG(lp)); \
1107 #define SMC_PUSH_DATA(lp, p, l) \
1109 if (SMC_32BIT(lp)) { \
1115 SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \
1118 if (SMC_CAN_USE_DATACS && lp->datacs) \
1119 __ioaddr = lp->datacs; \
1120 SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1123 SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \
1125 } else if (SMC_16BIT(lp)) \
1126 SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1127 else if (SMC_8BIT(lp)) \
1128 SMC_outsb(ioaddr, DATA_REG(lp), p, l); \
1131 #define SMC_PULL_DATA(lp, p, l) \
1133 if (SMC_32BIT(lp)) { \
1153 SMC_SET_PTR(lp, \
1156 if (SMC_CAN_USE_DATACS && lp->datacs) \
1157 __ioaddr = lp->datacs; \
1159 SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1160 } else if (SMC_16BIT(lp)) \
1161 SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1162 else if (SMC_8BIT(lp)) \
1163 SMC_insb(ioaddr, DATA_REG(lp), p, l); \