Lines Matching refs:bridge
63 /* PCI configuration space of a PCI-to-PCI bridge */
127 struct mvebu_sw_pci_bridge bridge;
354 if (port->bridge.iolimit < port->bridge.iobase ||
355 port->bridge.iolimitupper < port->bridge.iobaseupper ||
356 !(port->bridge.command & PCI_COMMAND_IO)) {
376 * We read the PCI-to-PCI bridge emulated registers, and
378 * window to setup, according to the PCI-to-PCI bridge
382 iobase = ((port->bridge.iobase & 0xF0) << 8) |
383 (port->bridge.iobaseupper << 16);
385 port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
386 (port->bridge.iolimitupper << 16)) -
397 if (port->bridge.memlimit < port->bridge.membase ||
398 !(port->bridge.command & PCI_COMMAND_MEMORY)) {
412 * We read the PCI-to-PCI bridge emulated registers, and
414 * window to setup, according to the PCI-to-PCI bridge
417 port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16);
419 (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
428 * Initialize the configuration space of the PCI-to-PCI bridge
433 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
435 memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
437 bridge->class = PCI_CLASS_BRIDGE_PCI;
438 bridge->vendor = PCI_VENDOR_ID_MARVELL;
439 bridge->device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16;
440 bridge->revision = mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff;
441 bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
442 bridge->cache_line_size = 0x10;
445 bridge->iobase = PCI_IO_RANGE_TYPE_32;
446 bridge->iolimit = PCI_IO_RANGE_TYPE_32;
450 * Read the configuration space of the PCI-to-PCI bridge associated to
456 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
460 *value = bridge->device << 16 | bridge->vendor;
464 *value = bridge->command;
468 *value = bridge->class << 16 | bridge->interface << 8 |
469 bridge->revision;
473 *value = bridge->bist << 24 | bridge->header_type << 16 |
474 bridge->latency_timer << 8 | bridge->cache_line_size;
478 *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4];
482 *value = (bridge->secondary_latency_timer << 24 |
483 bridge->subordinate_bus << 16 |
484 bridge->secondary_bus << 8 |
485 bridge->primary_bus);
490 *value = bridge->secondary_status << 16;
492 *value = (bridge->secondary_status << 16 |
493 bridge->iolimit << 8 |
494 bridge->iobase);
498 *value = (bridge->memlimit << 16 | bridge->membase);
506 *value = (bridge->iolimitupper << 16 | bridge->iobaseupper);
531 /* Write to the PCI-to-PCI bridge configuration space */
535 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
557 u32 old = bridge->command;
562 bridge->command = value & 0xffff;
563 if ((old ^ bridge->command) & PCI_COMMAND_IO)
565 if ((old ^ bridge->command) & PCI_COMMAND_MEMORY)
571 bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
580 bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
581 bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
586 bridge->membase = value & 0xffff;
587 bridge->memlimit = value >> 16;
592 bridge->iobaseupper = value & 0xffff;
593 bridge->iolimitupper = value >> 16;
598 bridge->primary_bus = value & 0xff;
599 bridge->secondary_bus = (value >> 8) & 0xff;
600 bridge->subordinate_bus = (value >> 16) & 0xff;
601 bridge->secondary_latency_timer = (value >> 24) & 0xff;
602 mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);
628 bus->number >= port->bridge.secondary_bus &&
629 bus->number <= port->bridge.subordinate_bus)
648 /* Access the emulated PCI-to-PCI bridge */
662 if (bus->number == port->bridge.secondary_bus &&
687 /* Access the emulated PCI-to-PCI bridge */
703 if (bus->number == port->bridge.secondary_bus &&
793 * On the PCI-to-PCI bridge side, the I/O windows must have at