56fab6e189441d714a2bfc8a64f3df9c0749dff7 |
|
17-Sep-2014 |
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
PCI: mvebu: Fix uninitialized variable in mvebu_get_tgt_attr() Geert Uytterhoeven reported a warning when building pci-mvebu: drivers/pci/host/pci-mvebu.c: In function 'mvebu_get_tgt_attr': drivers/pci/host/pci-mvebu.c:887:39: warning: 'rtype' may be used uninitialized in this function [-Wmaybe-uninitialized] if (slot == PCI_SLOT(devfn) && type == rtype) { ^ And indeed, the code of mvebu_get_tgt_attr() may lead to the usage of rtype when being uninitialized, even though it would only happen if we had entries other than I/O space and 32 bits memory space. This commit fixes that by simply skipping the current DT range being considered, if it doesn't match the resource type we're looking for. Reported-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v3.12+
|
505d8655f710b61c42ec74e3720dcf545f12a668 |
|
11-Jul-2014 |
Thierry Reding <treding@nvidia.com> |
PCI: mvebu: Fix GPL v2 license string typo Per license_is_gpl_compatible(), the MODULE_LICENSE() string for GPL v2 is "GPL v2", not "GPLv2". Use "GPL v2" so this module doesn't taint the kernel. [bhelgaas: changelog] Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
3c78bc61f5ef3bc87e7f94f67ec737d2273f120b |
|
19-Apr-2014 |
Ryan Desfosses <ryan@desfo.org> |
PCI: Whitespace cleanup Fix various whitespace errors. No functional change. [bhelgaas: fix other similar problems] Signed-off-by: Ryan Desfosses <ryan@desfo.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
9aa52850455f7e46bb9eb72ebb9d8a571bf11cce |
|
29-Apr-2014 |
Fabio Estevam <fabio.estevam@freescale.com> |
PCI: mvebu: Use '%pa' for printing 'phys_addr_t' type Fix the following build warning that happens when building multi_v7_defconfig with CONFIG_ARM_LPAE=y: drivers/pci/host/pci-mvebu.c:334:5: warning: format '%x' expects argument of type 'unsigned int', but argument 3 has type 'phys_addr_t' [-Wformat=] Fix the warning by using '%pa' to printing 'phys_addr_t' type. While at it, also use the more standard notation [mem 0x-0x] for memory region. [bhelgaas: make end address inclusive, remove extra spaces] Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jason Cooper <jason@lakedaemon.net> Reviewed-by: Jingoo Han <jg1.han@samsung.com>
|
85802bbe755725b5bf92386b8a52eb6d089b581e |
|
15-Apr-2014 |
Andrew Murray <amurray@embedded-bits.co.uk> |
PCI: mvebu: Remove unnecessary use of 'conf_lock' spinlock Serialization of configuration accesses is provided by 'pci_lock' in drivers/pci/access.c thus making the driver's 'conf_lock' superfluous. Signed-off-by: Andrew Murray <amurray@embedded-bits.co.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jason Cooper <jason@lakedaemon.net>
|
398f5d5e10b6b917cd9d35ef21d545b0afbada22 |
|
18-Apr-2014 |
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
PCI: mvebu: split PCIe BARs into multiple MBus windows when needed MBus windows are used on Marvell platforms to map certain peripherals in the physical address space. In the PCIe context, MBus windows are needed to map PCIe I/O and memory regions in the physical address. However, those MBus windows can only have power of two sizes, while PCIe BAR do not necessarily guarantee this. For this reason, the current pci-mvebu breaks on platforms where PCIe devices have BARs that don't sum up to a power of two size at the emulated bridge level. This commit fixes this by allowing the pci-mvebu driver to create multiple contiguous MBus windows (each having a power of two size) to cover a given PCIe BAR. To achieve this, two functions are added: mvebu_pcie_add_windows() and mvebu_pcie_del_windows() to respectively add and remove all the MBus windows that are needed to map the provided PCIe region base and size. The emulated PCI bridge code now calls those functions, instead of directly calling the mvebu-mbus driver functions. Fixes: 45361a4fe446 ('pci: PCIe driver for Marvell Armada 370/XP systems') Cc: <stable@vger.kernel.org> # v3.11+ Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1397823593-1932-8-git-send-email-thomas.petazzoni@free-electrons.com Tested-by: Neil Greatorex <neil@fatboyfat.co.uk> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
|
b6d07e0273d3296cfbdc88145b8a00ddbefb310a |
|
18-Apr-2014 |
Willy Tarreau <w@1wt.eu> |
PCI: mvebu: fix off-by-one in the computed size of the mbus windows mvebu_pcie_handle_membase_change() and mvebu_pcie_handle_iobase_change() do not correctly compute the window size. PCI uses an inclusive start/end address pair, which requires a +1 when converting to size. This only worked because a bug in the mbus driver allowed it to silently accept and round up bogus sizes. Fix this by adding one to the computed size. Fixes: 45361a4fe446 ('PCIe driver for Marvell Armada 370/XP systems') Cc: <stable@vger.kernel.org> # v3.11+ Signed-off-by: Willy Tarreau <w@1wt.eu> Reviewed-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1397823593-1932-5-git-send-email-thomas.petazzoni@free-electrons.com Tested-by: Neil Greatorex <neil@fatboyfat.co.uk> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
|
2613ba480fb7b40c67eea36d03c9946977828623 |
|
12-Feb-2014 |
Jason Gunthorpe <jgunthorpe@obsidianresearch.com> |
PCI: mvebu: Call request_resource() on the apertures It is typical for host drivers to request a resource for the aperture; once this is done the PCI core will properly populate resources for all BARs in the system. With this patch cat /proc/iomem will now show: e0000000-efffffff : PCI MEM 0000 e0000000-e00fffff : PCI Bus 0000:01 e0000000-e001ffff : 0000:01:00.0 Tested on Kirkwood. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jason Cooper <jason@lakedaemon.net>
|
4f4bde1df33bde076f53325bdf2c6430cf85e1bb |
|
14-Feb-2014 |
Jean-Jacques Hiblot <jjhiblot@traphandler.com> |
PCI: mvebu: Fix potential issue in range parsing The second parameter of of_read_number() is not the index, but a size. As it happens, in this case it may work just fine because of the conversion to u32 and the favorable endianness on this architecture. Fixes: 11be65472a427 ("PCI: mvebu: Adapt to the new device tree layout") Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@traphandler.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Jason Cooper <jason@lakedaemon.net> Cc: stable@vger.kernel.org # v3.12+
|
322a8e91844f4ae2093e0d3d8a318d0ef2596756 |
|
05-Feb-2014 |
Andrew Lunn <andrew@lunn.ch> |
PCI: mvebu: Use Device ID and revision from underlying endpoint Marvell SoCs place the SoC number into the PCIe endpoint device ID. The SoC stepping is placed into the PCIe revision. The old plat-orion PCIe driver allowed this information to be seen in user space with a simple lspci command. The new driver places a virtual PCI-PCI bridge on top of these endpoints. It has its own hard coded PCI device ID. Thus it is no longer possible to see what the SoC is using lspci. When initializing the PCI-PCI bridge, set its device ID and revision from the underlying endpoint, thus restoring this functionality. Debian would like to use this in order to aid installing the correct DTB file. Fixes: 45361a4fe4464 ("pci: PCIe driver for Marvell Armada 370/XP systems") Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Jason Cooper <jason@lakedaemon.net> Cc: stable@vger.kernel.org # v3.11+
|
a760d2fb2c700469f2578f980e30423bcba316ac |
|
05-Feb-2014 |
Andrew Lunn <andrew@lunn.ch> |
PCI: mvebu: Use Device ID and revision from underlying endpoint Marvell SoCs place the SoC number into the PCIe endpoint device ID. The SoC stepping is placed into the PCIe revision. The old plat-orion PCIe driver allowed this information to be seen in user space with a simple lspci command. The new driver places a virtual PCI-PCI bridge on top of these endpoints. It has its own hard coded PCI device ID. Thus it is no longer possible to see what the SoC is using lspci. When initializing the PCI-PCI bridge, set its device ID and revision from the underlying endpoint, thus restoring this functionality. Debian would like to use this in order to aid installing the correct DTB file. Fixes: 45361a4fe4464 ("pci: PCIe driver for Marvell Armada 370/XP systems") Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Jason Cooper <jason@lakedaemon.net> Cc: stable@vger.kernel.org # v3.11+
|
06489002a175680e18b4c0dd0beb6aff2a6d3781 |
|
27-Dec-2013 |
Jingoo Han <jg1.han@samsung.com> |
PCI: mvebu: Use max_t() instead of max(resource_size_t,) Use max_t() instead of max(resource_size_t,) in order to fix the following checkpatch warning. WARNING: max() should probably be max_t(resource_size_t, SZ_64K, size) WARNING: max() should probably be max_t(resource_size_t, SZ_1M, size) Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jason Cooper <jason@lakedaemon.net>
|
31e45ec3a4e73dcbeb51e03ab559812ba3e82cc2 |
|
26-Dec-2013 |
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
PCI: mvebu: Call pci_ioremap_io() at startup instead of dynamically The mvebu PCI host controller driver uses an emulated PCI-to-PCI bridge to leverage the core PCI kernel enumeration logic to dynamically create and remove the MBus windows needed to access the memory and I/O regions of each PCI interface. In the context of this PCI-to-PCI bridge emulation, the driver emulates all reads and writes to the PCI bridge registers. Upon a write to the registers configuring the I/O base and limit, the driver was creating the MBus window and calling pci_ioremap_io() to setup the mapping. However, it turns out that accesses to these registers are made in an IRQ disabled context, while pci_ioremap_io() is a potentially sleeping function. Not only this is wrong, but it is causing fairly loud warnings at boot time when the appropriate kernel hacking options are enabled. This patch solves this by moving the pci_ioremap_io() call to the startup of the driver. At this point, we don't know how many PCI interfaces will be enabled, so we are simply remapping the entire PCI I/O space to virtual addresses. This is reasonable since this I/O space is limited to 1 MB in size, and also because the MBus windows continue to be created in a dynamic fashion only when devices need them. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
339135ff1b5fca9a323ca7af67cebefedf50d4e7 |
|
19-Dec-2013 |
Sachin Kamat <sachin.kamat@linaro.org> |
PCI: mvebu: Remove redundant of_match_ptr mvebu_pcie_of_match_table is always compiled in. Hence of_match_ptr is not required. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
84f47190d6be1cb99cd4a680e1018080d93800a8 |
|
04-Dec-2013 |
Andrew Lunn <andrew@lunn.ch> |
PCI: mvebu: Remove duplicate of_clk_get_by_name() call Probably due to a merge conflict resolution gone bad, the PCI clock is got twice. Remove the redundant call of of_clk_get_by_name(). Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Jason Cooper <jason@lakedaemon.net>
|
641e674d6c0f974162c4c8cc0081c7ffc50b3911 |
|
26-Nov-2013 |
Jason Gunthorpe <jgunthorpe@obsidianresearch.com> |
PCI: mvebu: Support a bridge with no IO port window Make pcie-io-aperture and the IO port MBUS ID in ranges optional. If not provided the bridge reports to Linux that IO space mapping is not supported and refuses to configure an IO MBUS window. This allows both complete disable (do not specify pcie-io-aperture) and per-port disable (do not specify a IO target ranges entry for the port). Most PCIe devices these days do not require IO support to function, so having an option to disable it in the driver is useful. Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jason Cooper <jason@lakedaemon.net>
|
43a16f94445310800e39d54aaa534f2ce7dbe0a2 |
|
26-Nov-2013 |
Jason Gunthorpe <jgunthorpe@obsidianresearch.com> |
PCI: mvebu: Obey bridge PCI_COMMAND_MEM and PCI_COMMAND_IO bits When PCI_COMMAND_MEMORY/PCI_COMMAND_IO are cleared, the bridge should not allocate windows or even look at the window limit/base registers. Otherwise we may set up bogus windows while the PCI core code performs discovery. The core will leave PCI_COMMAND_IO cleared if it doesn't need an IO window. Have mvebu_pcie_handle_*_change respect the bits, and call the change function whenever the bits changes. Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jason Cooper <jason@lakedaemon.net>
|
f407dae76040c9529c2c83b1488dda4ffc54522c |
|
26-Nov-2013 |
Jason Gunthorpe <jgunthorpe@obsidianresearch.com> |
PCI: mvebu: Return 'unsupported' for Interrupt Line and Interrupt Pin The emulated bridge does not support interrupts, so it should return the value 0 for Interrupt Line and Interrupt Pin. This indicates that interrupts are not supported. Since Max_Lat and Min_Gnt are also in the same 32-bit word, we return 0 for them, which means "do not care." This corrects an error message from the kernel: pci 0000:00:01.0: of_irq_parse_pci() failed with rc=135 Which is due to the default return of 0xFFFFFFFF indicating that interrupts are supported. The error message regression was caused by 16b84e5a505 ("of/irq: Create of_irq_parse_and_map_pci() to consolidate arch code.") Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jason Cooper <jason@lakedaemon.net>
|
2850b05c9644d0f4c9df6cc77d628d7e0598a0cc |
|
26-Nov-2013 |
Jason Gunthorpe <jgunthorpe@obsidianresearch.com> |
PCI: mvebu: Drop writes to bridge Secondary Status register There are no writable bits in the secondary status register, only RO and RW1C (write-1-to-clear) bits. The driver never sets any of the RW1C bits, so the status register should always be 0, just remove the set from the write path. Someday the RW1C bits should be copied/cleared directly from registers in the HW. [bhelgaas: changelog tweaks] Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jason Cooper <jason@lakedaemon.net>
|
16b84e5a505c790538e534ad8dfda9c288691e40 |
|
19-Sep-2013 |
Grant Likely <grant.likely@linaro.org> |
of/irq: Create of_irq_parse_and_map_pci() to consolidate arch code. Several architectures open code effectively the same code block for finding and mapping PCI irqs. This patch consolidates it down to a single function. Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Michal Simek <monstr@monstr.eu> Cc: Russell King <linux@arm.linux.org.uk> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
e6d30ab1e7d1281784672c0fc2ffa385cfb7279e |
|
15-Sep-2013 |
Grant Likely <grant.likely@linaro.org> |
of/irq: simplify args to irq_create_of_mapping All the callers of irq_create_of_mapping() pass the contents of a struct of_phandle_args structure to the function. Since all the callers already have an of_phandle_args pointer, why not pass it directly to irq_create_of_mapping()? Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Michal Simek <monstr@monstr.eu> Acked-by: Tony Lindgren <tony@atomide.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
530210c7814e83564c7ca7bca8192515042c0b63 |
|
15-Sep-2013 |
Grant Likely <grant.likely@linaro.org> |
of/irq: Replace of_irq with of_phandle_args struct of_irq and struct of_phandle_args are exactly the same structure. This patch makes the kernel use of_phandle_args everywhere. This in itself isn't a big deal, but it makes some follow-on patches simpler. Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Michal Simek <monstr@monstr.eu> Acked-by: Tony Lindgren <tony@atomide.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
0c02c8007ea5554d028f99fd3e29fc201fdeeab3 |
|
19-Sep-2013 |
Grant Likely <grant.likely@linaro.org> |
of/irq: Rename of_irq_map_* functions to of_irq_parse_* The OF irq handling code has been overloading the term 'map' to refer to both parsing the data in the device tree and mapping it to the internal linux irq system. This is probably because the device tree does have the concept of an 'interrupt-map' function for translating interrupt references from one node to another, but 'map' is still confusing when the primary purpose of some of the functions are to parse the DT data. This patch renames all the of_irq_map_* functions to of_irq_parse_* which makes it clear that there is a difference between the parsing phase and the mapping phase. Kernel code can make use of just the parsing or just the mapping support as needed by the subsystem. The patch was generated mechanically with a handful of sed commands. Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Michal Simek <monstr@monstr.eu> Acked-by: Tony Lindgren <tony@atomide.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
f5072dfbac053200c8865c4fb15e4f020b7b5d1d |
|
17-Sep-2013 |
Jingoo Han <jg1.han@samsung.com> |
PCI: mvebu: make local functions static mvebu_pcie_add_bus(), mvebu_pcie_align_resource() are used only in this file. Thus, these local functions should be staticized in order to fix the following sparse warnings: drivers/pci/host/pci-mvebu.c:684:6: warning: symbol 'mvebu_pcie_add_bus' was not declared. Should it be static? drivers/pci/host/pci-mvebu.c:690:17: warning: symbol 'mvebu_pcie_align_resource' was not declared. Should it be static? Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
|
032b4c0cc321b7b14e4035997f6debd1b42cdbe2 |
|
04-Oct-2013 |
Seungwon Jeon <tgih.jun@samsung.com> |
PCI: mvebu: add I/O access wrappers This change adds wrapper functions for MMIO access to PCIe IP block. And some 8/16-bit access are replaced by 32-bit. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
|
9f352f0e6c0fa2dc608812df297769789b7ecc51 |
|
01-Oct-2013 |
Jason Gunthorpe <jgunthorpe@obsidianresearch.com> |
PCI: mvebu: Dynamically detect if the PEX link is up to enable hot plug Otherwise hotplugging the PEX doesn't work at all since the driver detects the link state at probe time. Simply replacing the two tests of haslink with a register read is enough to fix it. Tested on kirkwood with repeated plug/unplug of the link partner. Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
|
cc54ccd9a6966708c00ebd8a08acc3e627a432c5 |
|
13-Aug-2013 |
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> |
PCI: mvebu: add support for Marvell Dove SoCs This patch adds a compatible for the PCIe controller found on Marvell Dove SoCs. Binding documentation and Kconfig entry are also updated. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
|
52ba992e201f47b878019f268391aa0e27592906 |
|
13-Aug-2013 |
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> |
PCI: mvebu: add support for reset on GPIO This patch adds a check for DT passed reset-gpios property and deasserts/ asserts reset pin on probe/remove with configurable delay. Corresponding binding documentation is also updated. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
|
e5615c30c1c921dda957638ddf9c9437fcb7bb36 |
|
13-Aug-2013 |
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> |
PCI: mvebu: remove subsys_initcall This removes the subsys_initcall from the driver and converts it to a normal platform_driver. Also, drvdata is set and a remove functions is added to disable the clock and free resources. As pci driver removal currently is not supported, set .suppress_bind_attrs to permit unbinding. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
|
bf09b6ae588f7567bcf31d9eff313d4d9fdc664e |
|
13-Aug-2013 |
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> |
PCI: mvebu: increment nports only for registered ports The number of ports is probed by counting the number of available child nodes. Later on, the registration of a port can fail and cause a mismatch between the ->nports counter and registered ports. This patch modifies the counting strategy, to make ->nports represent the number of registered ports instead of the number of available childs. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
|
b42285f66f871a9898a0e79e2d74bc7e7a101995 |
|
13-Aug-2013 |
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> |
PCI: mvebu: move clock enable before register access The clock passed to PCI controller found on MVEBU SoCs may come from a clock gate. This requires the clock to be enabled before any registers are accessed. Therefore, move the clock enable before register iomap to ensure it is enabled. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
|
5b4deb6526bdea3b10b3717623aae171509e925f |
|
09-Aug-2013 |
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
PCI: mvebu: add support for MSI This commit adds support for Message Signaled Interrupts in the Marvell PCIe host controller. The work is very simple: it simply gets a reference to the msi_chip associated to the PCIe controller thanks to the msi-parent DT property, and stores this reference in the pci_bus structure. This is enough to let the Linux PCI core use the functions of msi_chip to setup and teardown MSIs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Thierry Reding <thierry.reding@gmail.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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f48fbf9c7e892d1b070affb273970d948b825939 |
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17-Jun-2013 |
Tushar Behera <tushar.behera@linaro.org> |
PCI: mvebu: Convert to use devm_ioremap_resource Commit 75096579c3ac ("lib: devres: Introduce devm_ioremap_resource()") introduced devm_ioremap_resource() and deprecated the use of devm_request_and_ioremap(). While at it, modify mvebu_pcie_map_registers() to propagate error code. Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
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b22503a9c3bd8a3512fa4daf2c6c456d12db34de |
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26-Jul-2013 |
Ezequiel Garcia <ezequiel.garcia@free-electrons.com> |
PCI: mvebu: Check valid base address before port setup This driver does not fail to probe when it cannot obtain a port base address. Therefore, add a check for NULL base address before setting up the port, which prevents a kernel panic in such cases. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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11be65472a427dcf7a11ab6e3e3628f1c6768b5b |
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26-Jul-2013 |
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
PCI: mvebu: Adapt to the new device tree layout The new device tree layout encodes the window's target ID and attribute in the PCIe controller node's ranges property. This allows to parse such entries to obtain such information and use the recently introduced MBus API to create the windows, instead of using the current name based scheme. Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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36dd1f3e02a4aed850a7b7318d7abd4f4d50528c |
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01-Aug-2013 |
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
PCI: mvebu: Disable prefetchable memory support in PCI-to-PCI bridge The Marvell PCIe driver uses an emulated PCI-to-PCI bridge to be able to dynamically set up MBus address decoding windows for PCI I/O and memory regions depending on the PCI devices enumerated by Linux. However, this emulated PCI-to-PCI bridge logic makes the Linux PCI core believe that prefetchable memory regions are supported (because the registers are read/write), while in fact no adress decoding window is ever created for such regions. Since the Marvell MBus address decoding windows do not distinguish memory regions and prefetchable memory regions, this patch takes a simple approach: change the PCI-to-PCI bridge emulation to let the Linux PCI core know that we don't support prefetchable memory regions. To achieve this, we simply make the prefetchable memory base a read-only register that always returns 0. Reading/writing all the other prefetchable memory related registers has no effect. This problem was originally reported by Finn Hoffmann <finn@uni-bremen.de>, who couldn't get a RTL8111/8168B PCI NIC working on the NSA310 Kirkwood platform after updating to 3.11-rc. The problem was that the PCI-to-PCI bridge emulation was making the Linux PCI core believe that we support prefetchable memory, so the Linux PCI core was only filling the prefetchable memory base and limit registers, which does not lead to a MBus window being created. The below patch has been confirmed by Finn Hoffmann to fix his problem on Kirkwood, and has otherwise been successfully tested on the Armada XP GP platform with a e1000e PCIe NIC and a Marvell SATA PCIe card. Reported-by: Finn Hoffmann <finn@uni-bremen.de> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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005625fc5d62220242ec488d112e0a97e7fcd7bc |
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15-May-2013 |
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
pci: mvebu: enable driver usage on Kirkwood We allow the pci-mvebu driver to be compiled on the Kirkwood platform, and add the 'marvell,kirkwood-pcie' as a compatible string supported by the driver. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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6eb237c41acc1cf00b3b1176ad4a0ed3f221d630 |
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23-May-2013 |
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
pci: mvebu: fix the emulation of the status register The status register of the PCI configuration space of PCI-to-PCI bridges contain some read-only bits, and so write-1-to-clear bits. So, the Linux PCI core sometimes writes 0xffff to this status register, and in the current PCI-to-PCI bridge emulation code of the Marvell driver, we do take all those 1s being written. Even the read-only bits are being overwritten. For now, all the read-only bits should be emulated to have the zero value. The other bits, that are write-1-to-clear bits are used to report various kind of errors, and are never set by the emulated bridge, so there is no need to support this write-1-to-clear bits mechanism. As a conclusion, the easiest solution is to simply emulate this status register by returning zero when read, and ignore the writes to it. This has two visible effects: * The devsel is no longer 'unknown' in, i.e Flags: bus master, 66MHz, user-definable features, ?? devsel, latency 0 becomes: Flags: bus master, 66MHz, user-definable features, fast devsel, latency 0 in lspci -v. This was caused by a value of 11b being read for devsel, which is an invalid value. This 11b value being read was due to a previous write of 0xffff into the status register. * The capability list is no longer broken, because we indicate to the Linux PCI core that we don't have a Capabilities Pointer in the PCI configuration space of this bridge. The following message is therefore no longer visible in lspci -v: Capabilities: [fc] <chain broken> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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197fc226d96623bf25237c480d46e9954b28a75e |
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23-May-2013 |
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
pci: mvebu: allow the enumeration of devices beyond physical bridges Until now, the Marvell PCIe driver was only allowing the enumeration of the devices in the secondary bus of the emulated PCI-to-PCI bridge. This works fine when a PCIe device is directly connected into a PCIe slot of the Marvell board. However, when the device connected in the PCIe slot is a physical PCIe bridge, beyond which a real PCIe device is connected, it no longer worked, as the driver was preventing the Linux PCI core from seeing such devices. This commit fixes that by ensuring that configuration transactions on subordinate busses are properly forwarded on the right PCIe interface. Thanks to this patch, a PCIe card beyond a PCIe bridge, itself beyond the emulated PCI-to-PCI bridge is properly detected, with the following layout: -[0000:00]-+-01.0-[01]----00.0 +-09.0-[02-07]----00.0-[03-07]--+-01.0-[04]-- | +-05.0-[05]-- | +-07.0-[06]-- | \-09.0-[07]----00.0 \-0a.0-[08]----00.0 Where the PCIe interface that sits beyond the emulated PCI-to-PCI bridge at 09.0 allows to access the secondary bus 02, on which there is a PCIe bridge that allows to access the 3 to 7 busses, that are subordinates to this bridge. And on one of this bus (bus 7), there is one real PCIe device connected. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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f4ac99011e542d06ea2bda10063502583c6d7991 |
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23-May-2013 |
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
pci: mvebu: no longer fake the slot location of downstream devices By default, the Marvell hardware, for each PCIe interface, exhibits the following devices: * On slot 0, a "Marvell Memory controller", identical on all PCIe interfaces, and which isn't useful when the Marvell SoC is the PCIe root complex (i.e, the normal case when we run Linux on the Marvell SoC). * On slot 1, the real PCIe card connected into the PCIe slot of the board. So, what the Marvell PCIe driver was doing in its PCI-to-PCI bridge emulation is that when the Linux PCI core was trying to access the device in slot 0, we were in fact forwarding the configuration transaction to the device in slot 1. For all other slots, we were telling the Linux PCI core that there was no device connected. However, new versions of bootloaders from Marvell change the default PCIe configuration, and make the real device appear in slot 0, and the "Marvell Memory controller" in slot 1. Therefore, this commit modifies the Marvell PCIe driver to adjust the PCIe hardware configuration to make sure that this behavior (real device in slot 0, "Marvell Memory controller" in slot 1) is the one we'll see regardless of what the bootloader has done. It allows to remove the little hack that was forwarding configuration transactions on slot 0 to slot 1, which is nice. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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3d9939c92efdd4ced672b94994959ca71b141cb8 |
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27-May-2013 |
Wei Yongjun <yongjun_wei@trendmicro.com.cn> |
pci: mvebu: fix return value check in mvebu_pcie_probe() In case of error, function of_clk_get_by_name() returns ERR_PTR() never returns NULL. The NULL test in the return value check should be replaced with IS_ERR(). Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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45361a4fe4464180815157654aabbd2afb4848ad |
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16-May-2013 |
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
pci: PCIe driver for Marvell Armada 370/XP systems This driver implements the support for the PCIe interfaces on the Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to cover earlier families of Marvell SoCs, such as Dove, Orion and Kirkwood. The driver implements the hw_pci operations needed by the core ARM PCI code to setup PCI devices and get their corresponding IRQs, and the pci_ops operations that are used by the PCI core to read/write the configuration space of PCI devices. Since the PCIe interfaces of Marvell SoCs are completely separate and not linked together in a bus, this driver sets up an emulated PCI host bridge, with one PCI-to-PCI bridge as child for each hardware PCIe interface. In addition, this driver enumerates the different PCIe slots, and for those having a device plugged in, it sets up the necessary address decoding windows, using the mvebu-mbus driver. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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