pci-mvebu.c revision 84f47190d6be1cb99cd4a680e1018080d93800a8
1/* 2 * PCIe driver for Marvell Armada 370 and Armada XP SoCs 3 * 4 * This file is licensed under the terms of the GNU General Public 5 * License version 2. This program is licensed "as is" without any 6 * warranty of any kind, whether express or implied. 7 */ 8 9#include <linux/kernel.h> 10#include <linux/pci.h> 11#include <linux/clk.h> 12#include <linux/delay.h> 13#include <linux/gpio.h> 14#include <linux/module.h> 15#include <linux/mbus.h> 16#include <linux/msi.h> 17#include <linux/slab.h> 18#include <linux/platform_device.h> 19#include <linux/of_address.h> 20#include <linux/of_irq.h> 21#include <linux/of_gpio.h> 22#include <linux/of_pci.h> 23#include <linux/of_platform.h> 24 25/* 26 * PCIe unit register offsets. 27 */ 28#define PCIE_DEV_ID_OFF 0x0000 29#define PCIE_CMD_OFF 0x0004 30#define PCIE_DEV_REV_OFF 0x0008 31#define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3)) 32#define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3)) 33#define PCIE_HEADER_LOG_4_OFF 0x0128 34#define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4)) 35#define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4)) 36#define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4)) 37#define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4)) 38#define PCIE_WIN5_CTRL_OFF 0x1880 39#define PCIE_WIN5_BASE_OFF 0x1884 40#define PCIE_WIN5_REMAP_OFF 0x188c 41#define PCIE_CONF_ADDR_OFF 0x18f8 42#define PCIE_CONF_ADDR_EN 0x80000000 43#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc)) 44#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) 45#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) 46#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8) 47#define PCIE_CONF_ADDR(bus, devfn, where) \ 48 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \ 49 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \ 50 PCIE_CONF_ADDR_EN) 51#define PCIE_CONF_DATA_OFF 0x18fc 52#define PCIE_MASK_OFF 0x1910 53#define PCIE_MASK_ENABLE_INTS 0x0f000000 54#define PCIE_CTRL_OFF 0x1a00 55#define PCIE_CTRL_X1_MODE 0x0001 56#define PCIE_STAT_OFF 0x1a04 57#define PCIE_STAT_BUS 0xff00 58#define PCIE_STAT_DEV 0x1f0000 59#define PCIE_STAT_LINK_DOWN BIT(0) 60#define PCIE_DEBUG_CTRL 0x1a60 61#define PCIE_DEBUG_SOFT_RESET BIT(20) 62 63/* 64 * This product ID is registered by Marvell, and used when the Marvell 65 * SoC is not the root complex, but an endpoint on the PCIe bus. It is 66 * therefore safe to re-use this PCI ID for our emulated PCI-to-PCI 67 * bridge. 68 */ 69#define MARVELL_EMULATED_PCI_PCI_BRIDGE_ID 0x7846 70 71/* PCI configuration space of a PCI-to-PCI bridge */ 72struct mvebu_sw_pci_bridge { 73 u16 vendor; 74 u16 device; 75 u16 command; 76 u16 class; 77 u8 interface; 78 u8 revision; 79 u8 bist; 80 u8 header_type; 81 u8 latency_timer; 82 u8 cache_line_size; 83 u32 bar[2]; 84 u8 primary_bus; 85 u8 secondary_bus; 86 u8 subordinate_bus; 87 u8 secondary_latency_timer; 88 u8 iobase; 89 u8 iolimit; 90 u16 secondary_status; 91 u16 membase; 92 u16 memlimit; 93 u16 iobaseupper; 94 u16 iolimitupper; 95 u8 cappointer; 96 u8 reserved1; 97 u16 reserved2; 98 u32 romaddr; 99 u8 intline; 100 u8 intpin; 101 u16 bridgectrl; 102}; 103 104struct mvebu_pcie_port; 105 106/* Structure representing all PCIe interfaces */ 107struct mvebu_pcie { 108 struct platform_device *pdev; 109 struct mvebu_pcie_port *ports; 110 struct msi_chip *msi; 111 struct resource io; 112 struct resource realio; 113 struct resource mem; 114 struct resource busn; 115 int nports; 116}; 117 118/* Structure representing one PCIe interface */ 119struct mvebu_pcie_port { 120 char *name; 121 void __iomem *base; 122 spinlock_t conf_lock; 123 u32 port; 124 u32 lane; 125 int devfn; 126 unsigned int mem_target; 127 unsigned int mem_attr; 128 unsigned int io_target; 129 unsigned int io_attr; 130 struct clk *clk; 131 int reset_gpio; 132 int reset_active_low; 133 char *reset_name; 134 struct mvebu_sw_pci_bridge bridge; 135 struct device_node *dn; 136 struct mvebu_pcie *pcie; 137 phys_addr_t memwin_base; 138 size_t memwin_size; 139 phys_addr_t iowin_base; 140 size_t iowin_size; 141}; 142 143static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg) 144{ 145 writel(val, port->base + reg); 146} 147 148static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg) 149{ 150 return readl(port->base + reg); 151} 152 153static inline bool mvebu_has_ioport(struct mvebu_pcie_port *port) 154{ 155 return port->io_target != -1 && port->io_attr != -1; 156} 157 158static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port) 159{ 160 return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN); 161} 162 163static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr) 164{ 165 u32 stat; 166 167 stat = mvebu_readl(port, PCIE_STAT_OFF); 168 stat &= ~PCIE_STAT_BUS; 169 stat |= nr << 8; 170 mvebu_writel(port, stat, PCIE_STAT_OFF); 171} 172 173static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr) 174{ 175 u32 stat; 176 177 stat = mvebu_readl(port, PCIE_STAT_OFF); 178 stat &= ~PCIE_STAT_DEV; 179 stat |= nr << 16; 180 mvebu_writel(port, stat, PCIE_STAT_OFF); 181} 182 183/* 184 * Setup PCIE BARs and Address Decode Wins: 185 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks 186 * WIN[0-3] -> DRAM bank[0-3] 187 */ 188static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port) 189{ 190 const struct mbus_dram_target_info *dram; 191 u32 size; 192 int i; 193 194 dram = mv_mbus_dram_info(); 195 196 /* First, disable and clear BARs and windows. */ 197 for (i = 1; i < 3; i++) { 198 mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i)); 199 mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i)); 200 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i)); 201 } 202 203 for (i = 0; i < 5; i++) { 204 mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i)); 205 mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i)); 206 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i)); 207 } 208 209 mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF); 210 mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF); 211 mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF); 212 213 /* Setup windows for DDR banks. Count total DDR size on the fly. */ 214 size = 0; 215 for (i = 0; i < dram->num_cs; i++) { 216 const struct mbus_dram_window *cs = dram->cs + i; 217 218 mvebu_writel(port, cs->base & 0xffff0000, 219 PCIE_WIN04_BASE_OFF(i)); 220 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i)); 221 mvebu_writel(port, 222 ((cs->size - 1) & 0xffff0000) | 223 (cs->mbus_attr << 8) | 224 (dram->mbus_dram_target_id << 4) | 1, 225 PCIE_WIN04_CTRL_OFF(i)); 226 227 size += cs->size; 228 } 229 230 /* Round up 'size' to the nearest power of two. */ 231 if ((size & (size - 1)) != 0) 232 size = 1 << fls(size); 233 234 /* Setup BAR[1] to all DRAM banks. */ 235 mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1)); 236 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1)); 237 mvebu_writel(port, ((size - 1) & 0xffff0000) | 1, 238 PCIE_BAR_CTRL_OFF(1)); 239} 240 241static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port) 242{ 243 u32 cmd, mask; 244 245 /* Point PCIe unit MBUS decode windows to DRAM space. */ 246 mvebu_pcie_setup_wins(port); 247 248 /* Master + slave enable. */ 249 cmd = mvebu_readl(port, PCIE_CMD_OFF); 250 cmd |= PCI_COMMAND_IO; 251 cmd |= PCI_COMMAND_MEMORY; 252 cmd |= PCI_COMMAND_MASTER; 253 mvebu_writel(port, cmd, PCIE_CMD_OFF); 254 255 /* Enable interrupt lines A-D. */ 256 mask = mvebu_readl(port, PCIE_MASK_OFF); 257 mask |= PCIE_MASK_ENABLE_INTS; 258 mvebu_writel(port, mask, PCIE_MASK_OFF); 259} 260 261static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port, 262 struct pci_bus *bus, 263 u32 devfn, int where, int size, u32 *val) 264{ 265 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), 266 PCIE_CONF_ADDR_OFF); 267 268 *val = mvebu_readl(port, PCIE_CONF_DATA_OFF); 269 270 if (size == 1) 271 *val = (*val >> (8 * (where & 3))) & 0xff; 272 else if (size == 2) 273 *val = (*val >> (8 * (where & 3))) & 0xffff; 274 275 return PCIBIOS_SUCCESSFUL; 276} 277 278static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port, 279 struct pci_bus *bus, 280 u32 devfn, int where, int size, u32 val) 281{ 282 u32 _val, shift = 8 * (where & 3); 283 284 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), 285 PCIE_CONF_ADDR_OFF); 286 _val = mvebu_readl(port, PCIE_CONF_DATA_OFF); 287 288 if (size == 4) 289 _val = val; 290 else if (size == 2) 291 _val = (_val & ~(0xffff << shift)) | ((val & 0xffff) << shift); 292 else if (size == 1) 293 _val = (_val & ~(0xff << shift)) | ((val & 0xff) << shift); 294 else 295 return PCIBIOS_BAD_REGISTER_NUMBER; 296 297 mvebu_writel(port, _val, PCIE_CONF_DATA_OFF); 298 299 return PCIBIOS_SUCCESSFUL; 300} 301 302static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port) 303{ 304 phys_addr_t iobase; 305 306 /* Are the new iobase/iolimit values invalid? */ 307 if (port->bridge.iolimit < port->bridge.iobase || 308 port->bridge.iolimitupper < port->bridge.iobaseupper || 309 !(port->bridge.command & PCI_COMMAND_IO)) { 310 311 /* If a window was configured, remove it */ 312 if (port->iowin_base) { 313 mvebu_mbus_del_window(port->iowin_base, 314 port->iowin_size); 315 port->iowin_base = 0; 316 port->iowin_size = 0; 317 } 318 319 return; 320 } 321 322 if (!mvebu_has_ioport(port)) { 323 dev_WARN(&port->pcie->pdev->dev, 324 "Attempt to set IO when IO is disabled\n"); 325 return; 326 } 327 328 /* 329 * We read the PCI-to-PCI bridge emulated registers, and 330 * calculate the base address and size of the address decoding 331 * window to setup, according to the PCI-to-PCI bridge 332 * specifications. iobase is the bus address, port->iowin_base 333 * is the CPU address. 334 */ 335 iobase = ((port->bridge.iobase & 0xF0) << 8) | 336 (port->bridge.iobaseupper << 16); 337 port->iowin_base = port->pcie->io.start + iobase; 338 port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) | 339 (port->bridge.iolimitupper << 16)) - 340 iobase); 341 342 mvebu_mbus_add_window_remap_by_id(port->io_target, port->io_attr, 343 port->iowin_base, port->iowin_size, 344 iobase); 345 346 pci_ioremap_io(iobase, port->iowin_base); 347} 348 349static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port) 350{ 351 /* Are the new membase/memlimit values invalid? */ 352 if (port->bridge.memlimit < port->bridge.membase || 353 !(port->bridge.command & PCI_COMMAND_MEMORY)) { 354 355 /* If a window was configured, remove it */ 356 if (port->memwin_base) { 357 mvebu_mbus_del_window(port->memwin_base, 358 port->memwin_size); 359 port->memwin_base = 0; 360 port->memwin_size = 0; 361 } 362 363 return; 364 } 365 366 /* 367 * We read the PCI-to-PCI bridge emulated registers, and 368 * calculate the base address and size of the address decoding 369 * window to setup, according to the PCI-to-PCI bridge 370 * specifications. 371 */ 372 port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16); 373 port->memwin_size = 374 (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) - 375 port->memwin_base; 376 377 mvebu_mbus_add_window_by_id(port->mem_target, port->mem_attr, 378 port->memwin_base, port->memwin_size); 379} 380 381/* 382 * Initialize the configuration space of the PCI-to-PCI bridge 383 * associated with the given PCIe interface. 384 */ 385static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port) 386{ 387 struct mvebu_sw_pci_bridge *bridge = &port->bridge; 388 389 memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge)); 390 391 bridge->class = PCI_CLASS_BRIDGE_PCI; 392 bridge->vendor = PCI_VENDOR_ID_MARVELL; 393 bridge->device = MARVELL_EMULATED_PCI_PCI_BRIDGE_ID; 394 bridge->header_type = PCI_HEADER_TYPE_BRIDGE; 395 bridge->cache_line_size = 0x10; 396 397 /* We support 32 bits I/O addressing */ 398 bridge->iobase = PCI_IO_RANGE_TYPE_32; 399 bridge->iolimit = PCI_IO_RANGE_TYPE_32; 400} 401 402/* 403 * Read the configuration space of the PCI-to-PCI bridge associated to 404 * the given PCIe interface. 405 */ 406static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port, 407 unsigned int where, int size, u32 *value) 408{ 409 struct mvebu_sw_pci_bridge *bridge = &port->bridge; 410 411 switch (where & ~3) { 412 case PCI_VENDOR_ID: 413 *value = bridge->device << 16 | bridge->vendor; 414 break; 415 416 case PCI_COMMAND: 417 *value = bridge->command; 418 break; 419 420 case PCI_CLASS_REVISION: 421 *value = bridge->class << 16 | bridge->interface << 8 | 422 bridge->revision; 423 break; 424 425 case PCI_CACHE_LINE_SIZE: 426 *value = bridge->bist << 24 | bridge->header_type << 16 | 427 bridge->latency_timer << 8 | bridge->cache_line_size; 428 break; 429 430 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1: 431 *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4]; 432 break; 433 434 case PCI_PRIMARY_BUS: 435 *value = (bridge->secondary_latency_timer << 24 | 436 bridge->subordinate_bus << 16 | 437 bridge->secondary_bus << 8 | 438 bridge->primary_bus); 439 break; 440 441 case PCI_IO_BASE: 442 if (!mvebu_has_ioport(port)) 443 *value = bridge->secondary_status << 16; 444 else 445 *value = (bridge->secondary_status << 16 | 446 bridge->iolimit << 8 | 447 bridge->iobase); 448 break; 449 450 case PCI_MEMORY_BASE: 451 *value = (bridge->memlimit << 16 | bridge->membase); 452 break; 453 454 case PCI_PREF_MEMORY_BASE: 455 *value = 0; 456 break; 457 458 case PCI_IO_BASE_UPPER16: 459 *value = (bridge->iolimitupper << 16 | bridge->iobaseupper); 460 break; 461 462 case PCI_ROM_ADDRESS1: 463 *value = 0; 464 break; 465 466 default: 467 *value = 0xffffffff; 468 return PCIBIOS_BAD_REGISTER_NUMBER; 469 } 470 471 if (size == 2) 472 *value = (*value >> (8 * (where & 3))) & 0xffff; 473 else if (size == 1) 474 *value = (*value >> (8 * (where & 3))) & 0xff; 475 476 return PCIBIOS_SUCCESSFUL; 477} 478 479/* Write to the PCI-to-PCI bridge configuration space */ 480static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port, 481 unsigned int where, int size, u32 value) 482{ 483 struct mvebu_sw_pci_bridge *bridge = &port->bridge; 484 u32 mask, reg; 485 int err; 486 487 if (size == 4) 488 mask = 0x0; 489 else if (size == 2) 490 mask = ~(0xffff << ((where & 3) * 8)); 491 else if (size == 1) 492 mask = ~(0xff << ((where & 3) * 8)); 493 else 494 return PCIBIOS_BAD_REGISTER_NUMBER; 495 496 err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, ®); 497 if (err) 498 return err; 499 500 value = (reg & mask) | value << ((where & 3) * 8); 501 502 switch (where & ~3) { 503 case PCI_COMMAND: 504 { 505 u32 old = bridge->command; 506 507 if (!mvebu_has_ioport(port)) 508 value &= ~PCI_COMMAND_IO; 509 510 bridge->command = value & 0xffff; 511 if ((old ^ bridge->command) & PCI_COMMAND_IO) 512 mvebu_pcie_handle_iobase_change(port); 513 if ((old ^ bridge->command) & PCI_COMMAND_MEMORY) 514 mvebu_pcie_handle_membase_change(port); 515 break; 516 } 517 518 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1: 519 bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value; 520 break; 521 522 case PCI_IO_BASE: 523 /* 524 * We also keep bit 1 set, it is a read-only bit that 525 * indicates we support 32 bits addressing for the 526 * I/O 527 */ 528 bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32; 529 bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32; 530 mvebu_pcie_handle_iobase_change(port); 531 break; 532 533 case PCI_MEMORY_BASE: 534 bridge->membase = value & 0xffff; 535 bridge->memlimit = value >> 16; 536 mvebu_pcie_handle_membase_change(port); 537 break; 538 539 case PCI_IO_BASE_UPPER16: 540 bridge->iobaseupper = value & 0xffff; 541 bridge->iolimitupper = value >> 16; 542 mvebu_pcie_handle_iobase_change(port); 543 break; 544 545 case PCI_PRIMARY_BUS: 546 bridge->primary_bus = value & 0xff; 547 bridge->secondary_bus = (value >> 8) & 0xff; 548 bridge->subordinate_bus = (value >> 16) & 0xff; 549 bridge->secondary_latency_timer = (value >> 24) & 0xff; 550 mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus); 551 break; 552 553 default: 554 break; 555 } 556 557 return PCIBIOS_SUCCESSFUL; 558} 559 560static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys) 561{ 562 return sys->private_data; 563} 564 565static struct mvebu_pcie_port * 566mvebu_pcie_find_port(struct mvebu_pcie *pcie, struct pci_bus *bus, 567 int devfn) 568{ 569 int i; 570 571 for (i = 0; i < pcie->nports; i++) { 572 struct mvebu_pcie_port *port = &pcie->ports[i]; 573 if (bus->number == 0 && port->devfn == devfn) 574 return port; 575 if (bus->number != 0 && 576 bus->number >= port->bridge.secondary_bus && 577 bus->number <= port->bridge.subordinate_bus) 578 return port; 579 } 580 581 return NULL; 582} 583 584/* PCI configuration space write function */ 585static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn, 586 int where, int size, u32 val) 587{ 588 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata); 589 struct mvebu_pcie_port *port; 590 unsigned long flags; 591 int ret; 592 593 port = mvebu_pcie_find_port(pcie, bus, devfn); 594 if (!port) 595 return PCIBIOS_DEVICE_NOT_FOUND; 596 597 /* Access the emulated PCI-to-PCI bridge */ 598 if (bus->number == 0) 599 return mvebu_sw_pci_bridge_write(port, where, size, val); 600 601 if (!mvebu_pcie_link_up(port)) 602 return PCIBIOS_DEVICE_NOT_FOUND; 603 604 /* 605 * On the secondary bus, we don't want to expose any other 606 * device than the device physically connected in the PCIe 607 * slot, visible in slot 0. In slot 1, there's a special 608 * Marvell device that only makes sense when the Armada is 609 * used as a PCIe endpoint. 610 */ 611 if (bus->number == port->bridge.secondary_bus && 612 PCI_SLOT(devfn) != 0) 613 return PCIBIOS_DEVICE_NOT_FOUND; 614 615 /* Access the real PCIe interface */ 616 spin_lock_irqsave(&port->conf_lock, flags); 617 ret = mvebu_pcie_hw_wr_conf(port, bus, devfn, 618 where, size, val); 619 spin_unlock_irqrestore(&port->conf_lock, flags); 620 621 return ret; 622} 623 624/* PCI configuration space read function */ 625static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, 626 int size, u32 *val) 627{ 628 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata); 629 struct mvebu_pcie_port *port; 630 unsigned long flags; 631 int ret; 632 633 port = mvebu_pcie_find_port(pcie, bus, devfn); 634 if (!port) { 635 *val = 0xffffffff; 636 return PCIBIOS_DEVICE_NOT_FOUND; 637 } 638 639 /* Access the emulated PCI-to-PCI bridge */ 640 if (bus->number == 0) 641 return mvebu_sw_pci_bridge_read(port, where, size, val); 642 643 if (!mvebu_pcie_link_up(port)) { 644 *val = 0xffffffff; 645 return PCIBIOS_DEVICE_NOT_FOUND; 646 } 647 648 /* 649 * On the secondary bus, we don't want to expose any other 650 * device than the device physically connected in the PCIe 651 * slot, visible in slot 0. In slot 1, there's a special 652 * Marvell device that only makes sense when the Armada is 653 * used as a PCIe endpoint. 654 */ 655 if (bus->number == port->bridge.secondary_bus && 656 PCI_SLOT(devfn) != 0) { 657 *val = 0xffffffff; 658 return PCIBIOS_DEVICE_NOT_FOUND; 659 } 660 661 /* Access the real PCIe interface */ 662 spin_lock_irqsave(&port->conf_lock, flags); 663 ret = mvebu_pcie_hw_rd_conf(port, bus, devfn, 664 where, size, val); 665 spin_unlock_irqrestore(&port->conf_lock, flags); 666 667 return ret; 668} 669 670static struct pci_ops mvebu_pcie_ops = { 671 .read = mvebu_pcie_rd_conf, 672 .write = mvebu_pcie_wr_conf, 673}; 674 675static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys) 676{ 677 struct mvebu_pcie *pcie = sys_to_pcie(sys); 678 int i; 679 680 if (resource_size(&pcie->realio) != 0) 681 pci_add_resource_offset(&sys->resources, &pcie->realio, 682 sys->io_offset); 683 pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset); 684 pci_add_resource(&sys->resources, &pcie->busn); 685 686 for (i = 0; i < pcie->nports; i++) { 687 struct mvebu_pcie_port *port = &pcie->ports[i]; 688 if (!port->base) 689 continue; 690 mvebu_pcie_setup_hw(port); 691 } 692 693 return 1; 694} 695 696static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys) 697{ 698 struct mvebu_pcie *pcie = sys_to_pcie(sys); 699 struct pci_bus *bus; 700 701 bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr, 702 &mvebu_pcie_ops, sys, &sys->resources); 703 if (!bus) 704 return NULL; 705 706 pci_scan_child_bus(bus); 707 708 return bus; 709} 710 711static void mvebu_pcie_add_bus(struct pci_bus *bus) 712{ 713 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata); 714 bus->msi = pcie->msi; 715} 716 717static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev, 718 const struct resource *res, 719 resource_size_t start, 720 resource_size_t size, 721 resource_size_t align) 722{ 723 if (dev->bus->number != 0) 724 return start; 725 726 /* 727 * On the PCI-to-PCI bridge side, the I/O windows must have at 728 * least a 64 KB size and be aligned on their size, and the 729 * memory windows must have at least a 1 MB size and be 730 * aligned on their size 731 */ 732 if (res->flags & IORESOURCE_IO) 733 return round_up(start, max((resource_size_t)SZ_64K, size)); 734 else if (res->flags & IORESOURCE_MEM) 735 return round_up(start, max((resource_size_t)SZ_1M, size)); 736 else 737 return start; 738} 739 740static void mvebu_pcie_enable(struct mvebu_pcie *pcie) 741{ 742 struct hw_pci hw; 743 744 memset(&hw, 0, sizeof(hw)); 745 746 hw.nr_controllers = 1; 747 hw.private_data = (void **)&pcie; 748 hw.setup = mvebu_pcie_setup; 749 hw.scan = mvebu_pcie_scan_bus; 750 hw.map_irq = of_irq_parse_and_map_pci; 751 hw.ops = &mvebu_pcie_ops; 752 hw.align_resource = mvebu_pcie_align_resource; 753 hw.add_bus = mvebu_pcie_add_bus; 754 755 pci_common_init(&hw); 756} 757 758/* 759 * Looks up the list of register addresses encoded into the reg = 760 * <...> property for one that matches the given port/lane. Once 761 * found, maps it. 762 */ 763static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev, 764 struct device_node *np, struct mvebu_pcie_port *port) 765{ 766 struct resource regs; 767 int ret = 0; 768 769 ret = of_address_to_resource(np, 0, ®s); 770 if (ret) 771 return ERR_PTR(ret); 772 773 return devm_ioremap_resource(&pdev->dev, ®s); 774} 775 776#define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03) 777#define DT_TYPE_IO 0x1 778#define DT_TYPE_MEM32 0x2 779#define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF) 780#define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF) 781 782static int mvebu_get_tgt_attr(struct device_node *np, int devfn, 783 unsigned long type, 784 unsigned int *tgt, 785 unsigned int *attr) 786{ 787 const int na = 3, ns = 2; 788 const __be32 *range; 789 int rlen, nranges, rangesz, pna, i; 790 791 *tgt = -1; 792 *attr = -1; 793 794 range = of_get_property(np, "ranges", &rlen); 795 if (!range) 796 return -EINVAL; 797 798 pna = of_n_addr_cells(np); 799 rangesz = pna + na + ns; 800 nranges = rlen / sizeof(__be32) / rangesz; 801 802 for (i = 0; i < nranges; i++) { 803 u32 flags = of_read_number(range, 1); 804 u32 slot = of_read_number(range, 2); 805 u64 cpuaddr = of_read_number(range + na, pna); 806 unsigned long rtype; 807 808 if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO) 809 rtype = IORESOURCE_IO; 810 else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32) 811 rtype = IORESOURCE_MEM; 812 813 if (slot == PCI_SLOT(devfn) && type == rtype) { 814 *tgt = DT_CPUADDR_TO_TARGET(cpuaddr); 815 *attr = DT_CPUADDR_TO_ATTR(cpuaddr); 816 return 0; 817 } 818 819 range += rangesz; 820 } 821 822 return -ENOENT; 823} 824 825static void mvebu_pcie_msi_enable(struct mvebu_pcie *pcie) 826{ 827 struct device_node *msi_node; 828 829 msi_node = of_parse_phandle(pcie->pdev->dev.of_node, 830 "msi-parent", 0); 831 if (!msi_node) 832 return; 833 834 pcie->msi = of_pci_find_msi_chip_by_node(msi_node); 835 836 if (pcie->msi) 837 pcie->msi->dev = &pcie->pdev->dev; 838} 839 840static int mvebu_pcie_probe(struct platform_device *pdev) 841{ 842 struct mvebu_pcie *pcie; 843 struct device_node *np = pdev->dev.of_node; 844 struct device_node *child; 845 int i, ret; 846 847 pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie), 848 GFP_KERNEL); 849 if (!pcie) 850 return -ENOMEM; 851 852 pcie->pdev = pdev; 853 platform_set_drvdata(pdev, pcie); 854 855 /* Get the PCIe memory and I/O aperture */ 856 mvebu_mbus_get_pcie_mem_aperture(&pcie->mem); 857 if (resource_size(&pcie->mem) == 0) { 858 dev_err(&pdev->dev, "invalid memory aperture size\n"); 859 return -EINVAL; 860 } 861 862 mvebu_mbus_get_pcie_io_aperture(&pcie->io); 863 864 if (resource_size(&pcie->io) != 0) { 865 pcie->realio.flags = pcie->io.flags; 866 pcie->realio.start = PCIBIOS_MIN_IO; 867 pcie->realio.end = min_t(resource_size_t, 868 IO_SPACE_LIMIT, 869 resource_size(&pcie->io)); 870 } else 871 pcie->realio = pcie->io; 872 873 /* Get the bus range */ 874 ret = of_pci_parse_bus_range(np, &pcie->busn); 875 if (ret) { 876 dev_err(&pdev->dev, "failed to parse bus-range property: %d\n", 877 ret); 878 return ret; 879 } 880 881 i = 0; 882 for_each_child_of_node(pdev->dev.of_node, child) { 883 if (!of_device_is_available(child)) 884 continue; 885 i++; 886 } 887 888 pcie->ports = devm_kzalloc(&pdev->dev, i * 889 sizeof(struct mvebu_pcie_port), 890 GFP_KERNEL); 891 if (!pcie->ports) 892 return -ENOMEM; 893 894 i = 0; 895 for_each_child_of_node(pdev->dev.of_node, child) { 896 struct mvebu_pcie_port *port = &pcie->ports[i]; 897 enum of_gpio_flags flags; 898 899 if (!of_device_is_available(child)) 900 continue; 901 902 port->pcie = pcie; 903 904 if (of_property_read_u32(child, "marvell,pcie-port", 905 &port->port)) { 906 dev_warn(&pdev->dev, 907 "ignoring PCIe DT node, missing pcie-port property\n"); 908 continue; 909 } 910 911 if (of_property_read_u32(child, "marvell,pcie-lane", 912 &port->lane)) 913 port->lane = 0; 914 915 port->name = kasprintf(GFP_KERNEL, "pcie%d.%d", 916 port->port, port->lane); 917 918 port->devfn = of_pci_get_devfn(child); 919 if (port->devfn < 0) 920 continue; 921 922 ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_MEM, 923 &port->mem_target, &port->mem_attr); 924 if (ret < 0) { 925 dev_err(&pdev->dev, "PCIe%d.%d: cannot get tgt/attr for mem window\n", 926 port->port, port->lane); 927 continue; 928 } 929 930 if (resource_size(&pcie->io) != 0) 931 mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_IO, 932 &port->io_target, &port->io_attr); 933 else { 934 port->io_target = -1; 935 port->io_attr = -1; 936 } 937 938 port->reset_gpio = of_get_named_gpio_flags(child, 939 "reset-gpios", 0, &flags); 940 if (gpio_is_valid(port->reset_gpio)) { 941 u32 reset_udelay = 20000; 942 943 port->reset_active_low = flags & OF_GPIO_ACTIVE_LOW; 944 port->reset_name = kasprintf(GFP_KERNEL, 945 "pcie%d.%d-reset", port->port, port->lane); 946 of_property_read_u32(child, "reset-delay-us", 947 &reset_udelay); 948 949 ret = devm_gpio_request_one(&pdev->dev, 950 port->reset_gpio, GPIOF_DIR_OUT, port->reset_name); 951 if (ret) { 952 if (ret == -EPROBE_DEFER) 953 return ret; 954 continue; 955 } 956 957 gpio_set_value(port->reset_gpio, 958 (port->reset_active_low) ? 1 : 0); 959 msleep(reset_udelay/1000); 960 } 961 962 port->clk = of_clk_get_by_name(child, NULL); 963 if (IS_ERR(port->clk)) { 964 dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n", 965 port->port, port->lane); 966 continue; 967 } 968 969 ret = clk_prepare_enable(port->clk); 970 if (ret) 971 continue; 972 973 port->base = mvebu_pcie_map_registers(pdev, child, port); 974 if (IS_ERR(port->base)) { 975 dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n", 976 port->port, port->lane); 977 port->base = NULL; 978 clk_disable_unprepare(port->clk); 979 continue; 980 } 981 982 mvebu_pcie_set_local_dev_nr(port, 1); 983 984 port->dn = child; 985 spin_lock_init(&port->conf_lock); 986 mvebu_sw_pci_bridge_init(port); 987 i++; 988 } 989 990 pcie->nports = i; 991 mvebu_pcie_msi_enable(pcie); 992 mvebu_pcie_enable(pcie); 993 994 return 0; 995} 996 997static const struct of_device_id mvebu_pcie_of_match_table[] = { 998 { .compatible = "marvell,armada-xp-pcie", }, 999 { .compatible = "marvell,armada-370-pcie", }, 1000 { .compatible = "marvell,dove-pcie", }, 1001 { .compatible = "marvell,kirkwood-pcie", }, 1002 {}, 1003}; 1004MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table); 1005 1006static struct platform_driver mvebu_pcie_driver = { 1007 .driver = { 1008 .owner = THIS_MODULE, 1009 .name = "mvebu-pcie", 1010 .of_match_table = 1011 of_match_ptr(mvebu_pcie_of_match_table), 1012 /* driver unloading/unbinding currently not supported */ 1013 .suppress_bind_attrs = true, 1014 }, 1015 .probe = mvebu_pcie_probe, 1016}; 1017module_platform_driver(mvebu_pcie_driver); 1018 1019MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); 1020MODULE_DESCRIPTION("Marvell EBU PCIe driver"); 1021MODULE_LICENSE("GPLv2"); 1022