Cross Reference: /drivers/tty/serial/fsl

Lines Matching refs:membase
288 	temp = readb(port->membase + UARTCR2);
290 	writeb(temp, port->membase + UARTCR2);
297 	temp = lpuart32_read(port->membase + UARTCTRL);
299 	lpuart32_write(temp, port->membase + UARTCTRL);
306 	temp = readb(port->membase + UARTCR2);
307 	writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
314 	temp = lpuart32_read(port->membase + UARTCTRL);
315 	lpuart32_write(temp & ~UARTCTRL_RE, port->membase + UARTCTRL);
352 		readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size) {
353 		writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
362 		writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_TDMAS,
363 			sport->port.membase + UARTCR5);
405 		writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_TDMAS,
406 				sport->port.membase + UARTCR5);
408 		writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_TDMAS,
409 				sport->port.membase + UARTCR5);
496 	temp = readb(sport->port.membase + UARTCR5);
497 	writeb(temp & ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
516 	temp = readb(sport->port.membase + UARTCR5);
517 	writeb(temp | UARTCR5_RDMAS, sport->port.membase + UARTCR5);
527 		(readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
528 		writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
545 	txcnt = lpuart32_read(sport->port.membase + UARTWATER);
549 		lpuart32_write(xmit->buf[xmit->tail], sport->port.membase + UARTDATA);
552 		txcnt = lpuart32_read(sport->port.membase + UARTWATER);
571 	temp = readb(port->membase + UARTCR2);
572 	writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
578 		if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
588 	temp = lpuart32_read(port->membase + UARTCTRL);
589 	lpuart32_write(temp | UARTCTRL_TIE, port->membase + UARTCTRL);
591 	if (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE)
604 			lpuart32_write(sport->port.x_char, sport->port.membase + UARTDATA);
606 			writeb(sport->port.x_char, sport->port.membase + UARTDR);
641 	while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
648 		sr = readb(sport->port.membase + UARTSR1);
649 		rx = readb(sport->port.membase + UARTDR);
704 	while (!(lpuart32_read(sport->port.membase + UARTFIFO) & UARTFIFO_RXEMPT)) {
711 		sr = lpuart32_read(sport->port.membase + UARTSTAT);
712 		rx = lpuart32_read(sport->port.membase + UARTDATA);
763 	sts = readb(sport->port.membase + UARTSR1);
772 		!(readb(sport->port.membase + UARTCR5) & UARTCR5_TDMAS)) {
787 	sts = lpuart32_read(sport->port.membase + UARTSTAT);
788 	rxcount = lpuart32_read(sport->port.membase + UARTWATER);
795 		!(lpuart32_read(sport->port.membase + UARTBAUD) & UARTBAUD_TDMAE))
798 	lpuart32_write(sts, sport->port.membase + UARTSTAT);
805 	return (readb(port->membase + UARTSR1) & UARTSR1_TC) ?
811 	return (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TC) ?
820 	reg = readb(port->membase + UARTMODEM);
835 	reg = lpuart32_read(port->membase + UARTMODIR);
849 	temp = readb(port->membase + UARTMODEM) &
858 	writeb(temp, port->membase + UARTMODEM);
865 	temp = lpuart32_read(port->membase + UARTMODIR) &
874 	lpuart32_write(temp, port->membase + UARTMODIR);
881 	temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
886 	writeb(temp, port->membase + UARTCR2);
893 	temp = lpuart32_read(port->membase + UARTCTRL) & ~UARTCTRL_SBK;
898 	lpuart32_write(temp, port->membase + UARTCTRL);
906 	cr2 = readb(sport->port.membase + UARTCR2);
910 	writeb(cr2, sport->port.membase + UARTCR2);
912 	val = readb(sport->port.membase + UARTPFIFO);
914 			sport->port.membase + UARTPFIFO);
918 			sport->port.membase + UARTCFIFO);
920 	writeb(0, sport->port.membase + UARTTWFIFO);
921 	writeb(1, sport->port.membase + UARTRWFIFO);
924 	writeb(cr2_saved, sport->port.membase + UARTCR2);
932 	ctrl = lpuart32_read(sport->port.membase + UARTCTRL);
936 	lpuart32_write(ctrl, sport->port.membase + UARTCTRL);
939 	val = lpuart32_read(sport->port.membase + UARTFIFO);
942 	lpuart32_write(val, sport->port.membase + UARTFIFO);
946 	lpuart32_write(val, sport->port.membase + UARTWATER);
949 	lpuart32_write(ctrl_saved, sport->port.membase + UARTCTRL);
1096 	temp = readb(sport->port.membase + UARTPFIFO);
1109 		temp = readb(port->membase + UARTCR5);
1110 		writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5);
1122 	temp = readb(sport->port.membase + UARTCR2);
1124 	writeb(temp, sport->port.membase + UARTCR2);
1138 	temp = lpuart32_read(sport->port.membase + UARTFIFO);
1155 	temp = lpuart32_read(sport->port.membase + UARTCTRL);
1158 	lpuart32_write(temp, sport->port.membase + UARTCTRL);
1173 	temp = readb(port->membase + UARTCR2);
1176 	writeb(temp, port->membase + UARTCR2);
1197 	temp = lpuart32_read(port->membase + UARTCTRL);
1200 	lpuart32_write(temp, port->membase + UARTCTRL);
1218 	cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1219 	old_cr2 = readb(sport->port.membase + UARTCR2);
1220 	cr4 = readb(sport->port.membase + UARTCR4);
1221 	bdh = readb(sport->port.membase + UARTBDH);
1222 	modem = readb(sport->port.membase + UARTMODEM);
1319 	while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1324 			sport->port.membase + UARTCR2);
1332 	writeb(cr4 | brfa, sport->port.membase + UARTCR4);
1333 	writeb(bdh, sport->port.membase + UARTBDH);
1334 	writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
1335 	writeb(cr1, sport->port.membase + UARTCR1);
1336 	writeb(modem, sport->port.membase + UARTMODEM);
1339 	writeb(old_cr2, sport->port.membase + UARTCR2);
1355 	ctrl = old_ctrl = lpuart32_read(sport->port.membase + UARTCTRL);
1356 	bd = lpuart32_read(sport->port.membase + UARTBAUD);
1357 	modem = lpuart32_read(sport->port.membase + UARTMODIR);
1443 	while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC))
1448 			sport->port.membase + UARTCTRL);
1455 	lpuart32_write(bd, sport->port.membase + UARTBAUD);
1456 	lpuart32_write(modem, sport->port.membase + UARTMODIR);
1457 	lpuart32_write(ctrl, sport->port.membase + UARTCTRL);
1545 	while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
1548 	writeb(ch, port->membase + UARTDR);
1553 	while (!(lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE))
1556 	lpuart32_write(ch, port->membase + UARTDATA);
1566 	cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
1569 	writeb(cr2, sport->port.membase + UARTCR2);
1574 	while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1577 	writeb(old_cr2, sport->port.membase + UARTCR2);
1587 	cr = old_cr = lpuart32_read(sport->port.membase + UARTCTRL);
1590 	lpuart32_write(cr, sport->port.membase + UARTCTRL);
1595 	while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC))
1598 	lpuart32_write(old_cr, sport->port.membase + UARTCTRL);
1612 	cr = readb(sport->port.membase + UARTCR2);
1619 	cr = readb(sport->port.membase + UARTCR1);
1634 	bdh = readb(sport->port.membase + UARTBDH);
1636 	bdl = readb(sport->port.membase + UARTBDL);
1640 	brfa = readb(sport->port.membase + UARTCR4);
1661 	cr = lpuart32_read(sport->port.membase + UARTCTRL);
1668 	cr = lpuart32_read(sport->port.membase + UARTCTRL);
1683 	bd = lpuart32_read(sport->port.membase + UARTBAUD);
1794 	sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
1795 	if (IS_ERR(sport->port.membase))
1796 		return PTR_ERR(sport->port.membase);