Searched defs:CMD2 (Results 1 - 2 of 2) sorted by relevance
| /drivers/video/backlight/ |
| H A D | tdo24m.c | 46 #define CMD2(x, x1, x2) ((2 << 30) | ((x) << 18) | 0x20000 |\ macro
60 CMD2(0xB8, 0xFF, 0xF9), /* Output Control */
68 CMD2(0xB8, 0x80, 0x02), /* Output Control */
94 CMD2(0xd0, 0x08, 0x04), /* Blanking period control (2) */
96 CMD2(0xd2, 0x14, 0x00), /* CKV 1,2 timing control */
97 CMD2(0xd3, 0x1a, 0x0f), /* OEV timing control */
98 CMD2(0xd4, 0x1f, 0xaf), /* ASW timing control (1) */
107 CMD2(0xd7, 0x08, 0x04), /* Blanking period control (2) */
109 CMD2(0xd9, 0x00, 0x08), /* CKV 1,2 timing control */
110 CMD2(
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| /drivers/net/ethernet/amd/ |
| H A D | amd8111e.h | 41 Registers CMD0, CMD2, CMD3,CMD7 and INTEN0 uses a write access technique called command style access. It allows the write to selected bits of this register without altering the bits that are not selected. Command style registers are divided into 4 bytes that can be written independently. Higher order bit of each byte is the value bit that specifies the value that will be written into the selected bits of register.
58 #define CMD2 0x50 /* Command2 register */ macro
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