Searched defs:MHZ (Results 1 - 11 of 11) sorted by relevance
| /drivers/net/can/softing/ |
| H A D | softing_cs.c | 37 #define MHZ (1000*1000) macro
44 .freq = 16 * MHZ, .max_brp = 32, .max_sjw = 4,
56 .freq = 16 * MHZ, .max_brp = 32, .max_sjw = 4,
68 .freq = 20 * MHZ, .max_brp = 32, .max_sjw = 4,
80 .freq = 24 * MHZ, .max_brp = 64, .max_sjw = 4,
92 .freq = 16 * MHZ, .max_brp = 64, .max_sjw = 4,
104 .freq = 20 * MHZ, .max_brp = 32, .max_sjw = 4,
116 .freq = 24 * MHZ, .max_brp = 64, .max_sjw = 4,
128 .freq = 16 * MHZ, .max_brp = 64, .max_sjw = 4,
140 .freq = 24 * MHZ,
[all...] |
| /drivers/clk/ |
| H A D | clk-nspire.c | 17 #define MHZ (1000 * 1000) macro
48 clk->base_clock = 48 * MHZ;
50 clk->base_clock = 6 * EXTRACT(val, CX_BASE) * MHZ;
59 clk->base_clock = 27 * MHZ;
61 clk->base_clock = (300 - 6 * EXTRACT(val, CLASSIC_BASE)) * MHZ;
136 info.base_clock / MHZ,
137 info.base_clock / info.base_cpu_ratio / MHZ,
138 info.base_clock / info.base_ahb_ratio / MHZ);
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| /drivers/phy/ |
| H A D | phy-samsung-usb2.h | 22 #define MHZ (KHZ * KHZ) macro
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| H A D | phy-exynos5-usbdrd.c | 122 #define MHZ (KHZ * KHZ) macro
196 case 10 * MHZ:
199 case 12 * MHZ:
205 case 20 * MHZ:
208 case 24 * MHZ:
211 case 50 * MHZ:
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| /drivers/clk/samsung/ |
| H A D | clk.h | 55 #define MHZ (1000 * 1000) macro
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| /drivers/spi/ |
| H A D | spi-ath79.c | 34 #define MHZ (1000 * 1000) macro
260 rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
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| /drivers/video/fbdev/exynos/ |
| H A D | exynos_mipi_dsi_common.c | 41 #define MHZ (1000 * 1000) macro
42 #define FIN_HZ (24 * MHZ)
44 #define DFIN_PLL_MIN_HZ (6 * MHZ)
45 #define DFIN_PLL_MAX_HZ (12 * MHZ)
47 #define DFVCO_MIN_HZ (500 * MHZ)
48 #define DFVCO_MAX_HZ (1000 * MHZ)
502 if (dfin_pll < 7 * MHZ)
504 else if (dfin_pll < 8 * MHZ)
506 else if (dfin_pll < 9 * MHZ)
508 else if (dfin_pll < 10 * MHZ)
[all...] |
| /drivers/clk/sirf/ |
| H A D | clk-common.c | 11 #define MHZ (KHZ * KHZ) macro
89 WARN_ON(fin % MHZ);
90 return fin / MHZ * nf / nr / od * MHZ;
104 rate = rate - rate % MHZ;
106 nf = rate / MHZ;
114 nr = fin / MHZ;
136 nf = rate / MHZ;
137 if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1))
141 BUG_ON(fin < MHZ);
[all...] |
| /drivers/gpu/drm/nouveau/core/subdev/clock/ |
| H A D | gk20a.c | 26 #define MHZ (1000 * 1000) macro
164 target_clk_f = rate * 2 / MHZ;
165 ref_clk_f = priv->parent_rate / MHZ;
259 target_freq = gk20a_pllg_calc_rate(priv) / MHZ;
358 priv->parent_rate / MHZ);
391 priv->parent_rate / MHZ);
449 priv->parent_rate / MHZ);
646 nv_info(priv, "parent clock rate: %d Mhz\n", priv->parent_rate / MHZ);
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| /drivers/mfd/ |
| H A D | sm501.c | 87 #define MHZ (1000 * 1000) macro
122 pll2 = 288 * MHZ;
127 #define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x)
145 pll2 = 336 * MHZ;
148 pll2 = 288 * MHZ;
151 pll2 = 240 * MHZ;
154 pll2 = 192 * MHZ;
158 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ;
161 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ;
[all...] |
| /drivers/gpu/drm/exynos/ |
| H A D | exynos_drm_dsi.c | 356 #ifndef MHZ
357 #define MHZ (1000*1000) macro
370 p_min = DIV_ROUND_UP(fin, (12 * MHZ));
371 p_max = fin / (6 * MHZ);
386 if (tmp < 500 * MHZ || tmp > 1000 * MHZ)
446 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
[all...] |
Completed in 227 milliseconds