1/* 2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 * DEALINGS IN THE SOFTWARE. 21 * 22 * Shamelessly ripped off from ChromeOS's gk20a/clk_pllg.c 23 * 24 */ 25 26#define MHZ (1000 * 1000) 27 28#define MASK(w) ((1 << w) - 1) 29 30#define SYS_GPCPLL_CFG_BASE 0x00137000 31#define GPC_BCASE_GPCPLL_CFG_BASE 0x00132800 32 33#define GPCPLL_CFG (SYS_GPCPLL_CFG_BASE + 0) 34#define GPCPLL_CFG_ENABLE BIT(0) 35#define GPCPLL_CFG_IDDQ BIT(1) 36#define GPCPLL_CFG_LOCK_DET_OFF BIT(4) 37#define GPCPLL_CFG_LOCK BIT(17) 38 39#define GPCPLL_COEFF (SYS_GPCPLL_CFG_BASE + 4) 40#define GPCPLL_COEFF_M_SHIFT 0 41#define GPCPLL_COEFF_M_WIDTH 8 42#define GPCPLL_COEFF_N_SHIFT 8 43#define GPCPLL_COEFF_N_WIDTH 8 44#define GPCPLL_COEFF_P_SHIFT 16 45#define GPCPLL_COEFF_P_WIDTH 6 46 47#define GPCPLL_CFG2 (SYS_GPCPLL_CFG_BASE + 0xc) 48#define GPCPLL_CFG2_SETUP2_SHIFT 16 49#define GPCPLL_CFG2_PLL_STEPA_SHIFT 24 50 51#define GPCPLL_CFG3 (SYS_GPCPLL_CFG_BASE + 0x18) 52#define GPCPLL_CFG3_PLL_STEPB_SHIFT 16 53 54#define GPCPLL_NDIV_SLOWDOWN (SYS_GPCPLL_CFG_BASE + 0x1c) 55#define GPCPLL_NDIV_SLOWDOWN_NDIV_LO_SHIFT 0 56#define GPCPLL_NDIV_SLOWDOWN_NDIV_MID_SHIFT 8 57#define GPCPLL_NDIV_SLOWDOWN_STEP_SIZE_LO2MID_SHIFT 16 58#define GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT 22 59#define GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT 31 60 61#define SEL_VCO (SYS_GPCPLL_CFG_BASE + 0x100) 62#define SEL_VCO_GPC2CLK_OUT_SHIFT 0 63 64#define GPC2CLK_OUT (SYS_GPCPLL_CFG_BASE + 0x250) 65#define GPC2CLK_OUT_SDIV14_INDIV4_WIDTH 1 66#define GPC2CLK_OUT_SDIV14_INDIV4_SHIFT 31 67#define GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 68#define GPC2CLK_OUT_VCODIV_WIDTH 6 69#define GPC2CLK_OUT_VCODIV_SHIFT 8 70#define GPC2CLK_OUT_VCODIV1 0 71#define GPC2CLK_OUT_VCODIV_MASK (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \ 72 GPC2CLK_OUT_VCODIV_SHIFT) 73#define GPC2CLK_OUT_BYPDIV_WIDTH 6 74#define GPC2CLK_OUT_BYPDIV_SHIFT 0 75#define GPC2CLK_OUT_BYPDIV31 0x3c 76#define GPC2CLK_OUT_INIT_MASK ((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << \ 77 GPC2CLK_OUT_SDIV14_INDIV4_SHIFT)\ 78 | (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << GPC2CLK_OUT_VCODIV_SHIFT)\ 79 | (MASK(GPC2CLK_OUT_BYPDIV_WIDTH) << GPC2CLK_OUT_BYPDIV_SHIFT)) 80#define GPC2CLK_OUT_INIT_VAL ((GPC2CLK_OUT_SDIV14_INDIV4_MODE << \ 81 GPC2CLK_OUT_SDIV14_INDIV4_SHIFT) \ 82 | (GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT) \ 83 | (GPC2CLK_OUT_BYPDIV31 << GPC2CLK_OUT_BYPDIV_SHIFT)) 84 85#define GPC_BCAST_NDIV_SLOWDOWN_DEBUG (GPC_BCASE_GPCPLL_CFG_BASE + 0xa0) 86#define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT 24 87#define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK \ 88 (0x1 << GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT) 89 90#include <subdev/clock.h> 91#include <subdev/timer.h> 92 93#ifdef __KERNEL__ 94#include <nouveau_platform.h> 95#endif 96 97static const u8 pl_to_div[] = { 98/* PL: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */ 99/* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32, 100}; 101 102/* All frequencies in Mhz */ 103struct gk20a_clk_pllg_params { 104 u32 min_vco, max_vco; 105 u32 min_u, max_u; 106 u32 min_m, max_m; 107 u32 min_n, max_n; 108 u32 min_pl, max_pl; 109}; 110 111static const struct gk20a_clk_pllg_params gk20a_pllg_params = { 112 .min_vco = 1000, .max_vco = 1700, 113 .min_u = 12, .max_u = 38, 114 .min_m = 1, .max_m = 255, 115 .min_n = 8, .max_n = 255, 116 .min_pl = 1, .max_pl = 32, 117}; 118 119struct gk20a_clock_priv { 120 struct nouveau_clock base; 121 const struct gk20a_clk_pllg_params *params; 122 u32 m, n, pl; 123 u32 parent_rate; 124}; 125#define to_gk20a_clock(base) container_of(base, struct gk20a_clock_priv, base) 126 127static void 128gk20a_pllg_read_mnp(struct gk20a_clock_priv *priv) 129{ 130 u32 val; 131 132 val = nv_rd32(priv, GPCPLL_COEFF); 133 priv->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); 134 priv->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH); 135 priv->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); 136} 137 138static u32 139gk20a_pllg_calc_rate(struct gk20a_clock_priv *priv) 140{ 141 u32 rate; 142 u32 divider; 143 144 rate = priv->parent_rate * priv->n; 145 divider = priv->m * pl_to_div[priv->pl]; 146 do_div(rate, divider); 147 148 return rate / 2; 149} 150 151static int 152gk20a_pllg_calc_mnp(struct gk20a_clock_priv *priv, unsigned long rate) 153{ 154 u32 target_clk_f, ref_clk_f, target_freq; 155 u32 min_vco_f, max_vco_f; 156 u32 low_pl, high_pl, best_pl; 157 u32 target_vco_f, vco_f; 158 u32 best_m, best_n; 159 u32 u_f; 160 u32 m, n, n2; 161 u32 delta, lwv, best_delta = ~0; 162 u32 pl; 163 164 target_clk_f = rate * 2 / MHZ; 165 ref_clk_f = priv->parent_rate / MHZ; 166 167 max_vco_f = priv->params->max_vco; 168 min_vco_f = priv->params->min_vco; 169 best_m = priv->params->max_m; 170 best_n = priv->params->min_n; 171 best_pl = priv->params->min_pl; 172 173 target_vco_f = target_clk_f + target_clk_f / 50; 174 if (max_vco_f < target_vco_f) 175 max_vco_f = target_vco_f; 176 177 /* min_pl <= high_pl <= max_pl */ 178 high_pl = (max_vco_f + target_vco_f - 1) / target_vco_f; 179 high_pl = min(high_pl, priv->params->max_pl); 180 high_pl = max(high_pl, priv->params->min_pl); 181 182 /* min_pl <= low_pl <= max_pl */ 183 low_pl = min_vco_f / target_vco_f; 184 low_pl = min(low_pl, priv->params->max_pl); 185 low_pl = max(low_pl, priv->params->min_pl); 186 187 /* Find Indices of high_pl and low_pl */ 188 for (pl = 0; pl < ARRAY_SIZE(pl_to_div) - 1; pl++) { 189 if (pl_to_div[pl] >= low_pl) { 190 low_pl = pl; 191 break; 192 } 193 } 194 for (pl = 0; pl < ARRAY_SIZE(pl_to_div) - 1; pl++) { 195 if (pl_to_div[pl] >= high_pl) { 196 high_pl = pl; 197 break; 198 } 199 } 200 201 nv_debug(priv, "low_PL %d(div%d), high_PL %d(div%d)", low_pl, 202 pl_to_div[low_pl], high_pl, pl_to_div[high_pl]); 203 204 /* Select lowest possible VCO */ 205 for (pl = low_pl; pl <= high_pl; pl++) { 206 target_vco_f = target_clk_f * pl_to_div[pl]; 207 for (m = priv->params->min_m; m <= priv->params->max_m; m++) { 208 u_f = ref_clk_f / m; 209 210 if (u_f < priv->params->min_u) 211 break; 212 if (u_f > priv->params->max_u) 213 continue; 214 215 n = (target_vco_f * m) / ref_clk_f; 216 n2 = ((target_vco_f * m) + (ref_clk_f - 1)) / ref_clk_f; 217 218 if (n > priv->params->max_n) 219 break; 220 221 for (; n <= n2; n++) { 222 if (n < priv->params->min_n) 223 continue; 224 if (n > priv->params->max_n) 225 break; 226 227 vco_f = ref_clk_f * n / m; 228 229 if (vco_f >= min_vco_f && vco_f <= max_vco_f) { 230 lwv = (vco_f + (pl_to_div[pl] / 2)) 231 / pl_to_div[pl]; 232 delta = abs(lwv - target_clk_f); 233 234 if (delta < best_delta) { 235 best_delta = delta; 236 best_m = m; 237 best_n = n; 238 best_pl = pl; 239 240 if (best_delta == 0) 241 goto found_match; 242 } 243 } 244 } 245 } 246 } 247 248found_match: 249 WARN_ON(best_delta == ~0); 250 251 if (best_delta != 0) 252 nv_debug(priv, "no best match for target @ %dMHz on gpc_pll", 253 target_clk_f); 254 255 priv->m = best_m; 256 priv->n = best_n; 257 priv->pl = best_pl; 258 259 target_freq = gk20a_pllg_calc_rate(priv) / MHZ; 260 261 nv_debug(priv, "actual target freq %d MHz, M %d, N %d, PL %d(div%d)\n", 262 target_freq, priv->m, priv->n, priv->pl, pl_to_div[priv->pl]); 263 264 return 0; 265} 266 267static int 268gk20a_pllg_slide(struct gk20a_clock_priv *priv, u32 n) 269{ 270 u32 val; 271 int ramp_timeout; 272 273 /* get old coefficients */ 274 val = nv_rd32(priv, GPCPLL_COEFF); 275 /* do nothing if NDIV is the same */ 276 if (n == ((val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH))) 277 return 0; 278 279 /* setup */ 280 nv_mask(priv, GPCPLL_CFG2, 0xff << GPCPLL_CFG2_PLL_STEPA_SHIFT, 281 0x2b << GPCPLL_CFG2_PLL_STEPA_SHIFT); 282 nv_mask(priv, GPCPLL_CFG3, 0xff << GPCPLL_CFG3_PLL_STEPB_SHIFT, 283 0xb << GPCPLL_CFG3_PLL_STEPB_SHIFT); 284 285 /* pll slowdown mode */ 286 nv_mask(priv, GPCPLL_NDIV_SLOWDOWN, 287 BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT), 288 BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT)); 289 290 /* new ndiv ready for ramp */ 291 val = nv_rd32(priv, GPCPLL_COEFF); 292 val &= ~(MASK(GPCPLL_COEFF_N_WIDTH) << GPCPLL_COEFF_N_SHIFT); 293 val |= (n & MASK(GPCPLL_COEFF_N_WIDTH)) << GPCPLL_COEFF_N_SHIFT; 294 udelay(1); 295 nv_wr32(priv, GPCPLL_COEFF, val); 296 297 /* dynamic ramp to new ndiv */ 298 val = nv_rd32(priv, GPCPLL_NDIV_SLOWDOWN); 299 val |= 0x1 << GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT; 300 udelay(1); 301 nv_wr32(priv, GPCPLL_NDIV_SLOWDOWN, val); 302 303 for (ramp_timeout = 500; ramp_timeout > 0; ramp_timeout--) { 304 udelay(1); 305 val = nv_rd32(priv, GPC_BCAST_NDIV_SLOWDOWN_DEBUG); 306 if (val & GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK) 307 break; 308 } 309 310 /* exit slowdown mode */ 311 nv_mask(priv, GPCPLL_NDIV_SLOWDOWN, 312 BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT) | 313 BIT(GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT), 0); 314 nv_rd32(priv, GPCPLL_NDIV_SLOWDOWN); 315 316 if (ramp_timeout <= 0) { 317 nv_error(priv, "gpcpll dynamic ramp timeout\n"); 318 return -ETIMEDOUT; 319 } 320 321 return 0; 322} 323 324static void 325_gk20a_pllg_enable(struct gk20a_clock_priv *priv) 326{ 327 nv_mask(priv, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE); 328 nv_rd32(priv, GPCPLL_CFG); 329} 330 331static void 332_gk20a_pllg_disable(struct gk20a_clock_priv *priv) 333{ 334 nv_mask(priv, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0); 335 nv_rd32(priv, GPCPLL_CFG); 336} 337 338static int 339_gk20a_pllg_program_mnp(struct gk20a_clock_priv *priv, bool allow_slide) 340{ 341 u32 val, cfg; 342 u32 m_old, pl_old, n_lo; 343 344 /* get old coefficients */ 345 val = nv_rd32(priv, GPCPLL_COEFF); 346 m_old = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); 347 pl_old = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); 348 349 /* do NDIV slide if there is no change in M and PL */ 350 cfg = nv_rd32(priv, GPCPLL_CFG); 351 if (allow_slide && priv->m == m_old && priv->pl == pl_old && 352 (cfg & GPCPLL_CFG_ENABLE)) { 353 return gk20a_pllg_slide(priv, priv->n); 354 } 355 356 /* slide down to NDIV_LO */ 357 n_lo = DIV_ROUND_UP(m_old * priv->params->min_vco, 358 priv->parent_rate / MHZ); 359 if (allow_slide && (cfg & GPCPLL_CFG_ENABLE)) { 360 int ret = gk20a_pllg_slide(priv, n_lo); 361 362 if (ret) 363 return ret; 364 } 365 366 /* split FO-to-bypass jump in halfs by setting out divider 1:2 */ 367 nv_mask(priv, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK, 368 0x2 << GPC2CLK_OUT_VCODIV_SHIFT); 369 370 /* put PLL in bypass before programming it */ 371 val = nv_rd32(priv, SEL_VCO); 372 val &= ~(BIT(SEL_VCO_GPC2CLK_OUT_SHIFT)); 373 udelay(2); 374 nv_wr32(priv, SEL_VCO, val); 375 376 /* get out from IDDQ */ 377 val = nv_rd32(priv, GPCPLL_CFG); 378 if (val & GPCPLL_CFG_IDDQ) { 379 val &= ~GPCPLL_CFG_IDDQ; 380 nv_wr32(priv, GPCPLL_CFG, val); 381 nv_rd32(priv, GPCPLL_CFG); 382 udelay(2); 383 } 384 385 _gk20a_pllg_disable(priv); 386 387 nv_debug(priv, "%s: m=%d n=%d pl=%d\n", __func__, priv->m, priv->n, 388 priv->pl); 389 390 n_lo = DIV_ROUND_UP(priv->m * priv->params->min_vco, 391 priv->parent_rate / MHZ); 392 val = priv->m << GPCPLL_COEFF_M_SHIFT; 393 val |= (allow_slide ? n_lo : priv->n) << GPCPLL_COEFF_N_SHIFT; 394 val |= priv->pl << GPCPLL_COEFF_P_SHIFT; 395 nv_wr32(priv, GPCPLL_COEFF, val); 396 397 _gk20a_pllg_enable(priv); 398 399 val = nv_rd32(priv, GPCPLL_CFG); 400 if (val & GPCPLL_CFG_LOCK_DET_OFF) { 401 val &= ~GPCPLL_CFG_LOCK_DET_OFF; 402 nv_wr32(priv, GPCPLL_CFG, val); 403 } 404 405 if (!nouveau_timer_wait_eq(priv, 300000, GPCPLL_CFG, GPCPLL_CFG_LOCK, 406 GPCPLL_CFG_LOCK)) { 407 nv_error(priv, "%s: timeout waiting for pllg lock\n", __func__); 408 return -ETIMEDOUT; 409 } 410 411 /* switch to VCO mode */ 412 nv_mask(priv, SEL_VCO, 0, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT)); 413 414 /* restore out divider 1:1 */ 415 val = nv_rd32(priv, GPC2CLK_OUT); 416 val &= ~GPC2CLK_OUT_VCODIV_MASK; 417 udelay(2); 418 nv_wr32(priv, GPC2CLK_OUT, val); 419 420 /* slide up to new NDIV */ 421 return allow_slide ? gk20a_pllg_slide(priv, priv->n) : 0; 422} 423 424static int 425gk20a_pllg_program_mnp(struct gk20a_clock_priv *priv) 426{ 427 int err; 428 429 err = _gk20a_pllg_program_mnp(priv, true); 430 if (err) 431 err = _gk20a_pllg_program_mnp(priv, false); 432 433 return err; 434} 435 436static void 437gk20a_pllg_disable(struct gk20a_clock_priv *priv) 438{ 439 u32 val; 440 441 /* slide to VCO min */ 442 val = nv_rd32(priv, GPCPLL_CFG); 443 if (val & GPCPLL_CFG_ENABLE) { 444 u32 coeff, m, n_lo; 445 446 coeff = nv_rd32(priv, GPCPLL_COEFF); 447 m = (coeff >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); 448 n_lo = DIV_ROUND_UP(m * priv->params->min_vco, 449 priv->parent_rate / MHZ); 450 gk20a_pllg_slide(priv, n_lo); 451 } 452 453 /* put PLL in bypass before disabling it */ 454 nv_mask(priv, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0); 455 456 _gk20a_pllg_disable(priv); 457} 458 459#define GK20A_CLK_GPC_MDIV 1000 460 461static struct nouveau_clocks 462gk20a_domains[] = { 463 { nv_clk_src_crystal, 0xff }, 464 { nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV }, 465 { nv_clk_src_max } 466}; 467 468static struct nouveau_pstate 469gk20a_pstates[] = { 470 { 471 .base = { 472 .domain[nv_clk_src_gpc] = 72000, 473 }, 474 }, 475 { 476 .base = { 477 .domain[nv_clk_src_gpc] = 108000, 478 }, 479 }, 480 { 481 .base = { 482 .domain[nv_clk_src_gpc] = 180000, 483 }, 484 }, 485 { 486 .base = { 487 .domain[nv_clk_src_gpc] = 252000, 488 }, 489 }, 490 { 491 .base = { 492 .domain[nv_clk_src_gpc] = 324000, 493 }, 494 }, 495 { 496 .base = { 497 .domain[nv_clk_src_gpc] = 396000, 498 }, 499 }, 500 { 501 .base = { 502 .domain[nv_clk_src_gpc] = 468000, 503 }, 504 }, 505 { 506 .base = { 507 .domain[nv_clk_src_gpc] = 540000, 508 }, 509 }, 510 { 511 .base = { 512 .domain[nv_clk_src_gpc] = 612000, 513 }, 514 }, 515 { 516 .base = { 517 .domain[nv_clk_src_gpc] = 648000, 518 }, 519 }, 520 { 521 .base = { 522 .domain[nv_clk_src_gpc] = 684000, 523 }, 524 }, 525 { 526 .base = { 527 .domain[nv_clk_src_gpc] = 708000, 528 }, 529 }, 530 { 531 .base = { 532 .domain[nv_clk_src_gpc] = 756000, 533 }, 534 }, 535 { 536 .base = { 537 .domain[nv_clk_src_gpc] = 804000, 538 }, 539 }, 540 { 541 .base = { 542 .domain[nv_clk_src_gpc] = 852000, 543 }, 544 }, 545}; 546 547static int 548gk20a_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) 549{ 550 struct gk20a_clock_priv *priv = (void *)clk; 551 552 switch (src) { 553 case nv_clk_src_crystal: 554 return nv_device(clk)->crystal; 555 case nv_clk_src_gpc: 556 gk20a_pllg_read_mnp(priv); 557 return gk20a_pllg_calc_rate(priv) / GK20A_CLK_GPC_MDIV; 558 default: 559 nv_error(clk, "invalid clock source %d\n", src); 560 return -EINVAL; 561 } 562} 563 564static int 565gk20a_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) 566{ 567 struct gk20a_clock_priv *priv = (void *)clk; 568 569 return gk20a_pllg_calc_mnp(priv, cstate->domain[nv_clk_src_gpc] * 570 GK20A_CLK_GPC_MDIV); 571} 572 573static int 574gk20a_clock_prog(struct nouveau_clock *clk) 575{ 576 struct gk20a_clock_priv *priv = (void *)clk; 577 578 return gk20a_pllg_program_mnp(priv); 579} 580 581static void 582gk20a_clock_tidy(struct nouveau_clock *clk) 583{ 584} 585 586static int 587gk20a_clock_fini(struct nouveau_object *object, bool suspend) 588{ 589 struct gk20a_clock_priv *priv = (void *)object; 590 int ret; 591 592 ret = nouveau_clock_fini(&priv->base, false); 593 594 gk20a_pllg_disable(priv); 595 596 return ret; 597} 598 599static int 600gk20a_clock_init(struct nouveau_object *object) 601{ 602 struct gk20a_clock_priv *priv = (void *)object; 603 int ret; 604 605 nv_mask(priv, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK, GPC2CLK_OUT_INIT_VAL); 606 607 ret = nouveau_clock_init(&priv->base); 608 if (ret) 609 return ret; 610 611 ret = gk20a_clock_prog(&priv->base); 612 if (ret) { 613 nv_error(priv, "cannot initialize clock\n"); 614 return ret; 615 } 616 617 return 0; 618} 619 620static int 621gk20a_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 622 struct nouveau_oclass *oclass, void *data, u32 size, 623 struct nouveau_object **pobject) 624{ 625 struct gk20a_clock_priv *priv; 626 struct nouveau_platform_device *plat; 627 int ret; 628 int i; 629 630 /* Finish initializing the pstates */ 631 for (i = 0; i < ARRAY_SIZE(gk20a_pstates); i++) { 632 INIT_LIST_HEAD(&gk20a_pstates[i].list); 633 gk20a_pstates[i].pstate = i + 1; 634 } 635 636 ret = nouveau_clock_create(parent, engine, oclass, gk20a_domains, 637 gk20a_pstates, ARRAY_SIZE(gk20a_pstates), true, &priv); 638 *pobject = nv_object(priv); 639 if (ret) 640 return ret; 641 642 priv->params = &gk20a_pllg_params; 643 644 plat = nv_device_to_platform(nv_device(parent)); 645 priv->parent_rate = clk_get_rate(plat->gpu->clk); 646 nv_info(priv, "parent clock rate: %d Mhz\n", priv->parent_rate / MHZ); 647 648 priv->base.read = gk20a_clock_read; 649 priv->base.calc = gk20a_clock_calc; 650 priv->base.prog = gk20a_clock_prog; 651 priv->base.tidy = gk20a_clock_tidy; 652 653 return 0; 654} 655 656struct nouveau_oclass 657gk20a_clock_oclass = { 658 .handle = NV_SUBDEV(CLOCK, 0xea), 659 .ofuncs = &(struct nouveau_ofuncs) { 660 .ctor = gk20a_clock_ctor, 661 .dtor = _nouveau_subdev_dtor, 662 .init = gk20a_clock_init, 663 .fini = gk20a_clock_fini, 664 }, 665}; 666