| /arch/blackfin/lib/ |
| H A D | strcpy.S | 25 P0 = R0 ; /* dst*/ define
30 B [P0++] = R1;
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| H A D | ins.S | 76 P0 = R0; /* P0 = port */ \ define
92 R0 = [P0]; \
97 R0 = W[P0]; \
102 R0 = W[P0]; \
109 R0 = B[P0]; \
114 R0 = [P0]; \
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| H A D | memchr.S | 22 P0 = R0; /* P0 = address */ define
32 R3 = B[P0++](Z);
43 R0 = P0;
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| H A D | strcmp.S | 27 P0 = R0 ; /* s1 */ define
31 R0 = B[P0++] (Z); /* get *s1 */
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| H A D | strncmp.S | 28 P0 = R0 ; /* s1 */ define
31 R0 = B[P0++] (Z); /* get *s1 */
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| H A D | memcpy.S | 35 P0 = R0 ; /* dst*/ define
66 B[P0++] = R3;
78 [P0++] = R3;
84 MNOP || [P0++] = R3 || R3 = [I1++];
86 [P0++] = R3;
101 B[P0++] = R1;
112 P0 = P0 + P2; define
113 P0 += -1;
120 B[P0
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| H A D | memset.S | 27 P0 = R0 ; /* P0 = address */ define
47 [P0++] = R2;
49 CC = P0 == P2;
55 R3 = P0; /* current position */
66 B[P0++] = R1;
76 R0 = P0; /* Recover return address */
78 B[P0++] = R1;
83 B[P0++] = R1;
84 B[P0
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| H A D | outs.S | 18 P0 = R0; /* P0 = port */ define
24 .Llong_loop_e: [P0] = R0;
31 P0 = R0; /* P0 = port */ define
37 .Lword_loop_e: W[P0] = R0;
44 P0 = R0; /* P0 = port */ define
50 .Lbyte_loop_e: B[P0] = R0;
57 P0 define
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| H A D | memcmp.S | 23 P0 = R0; /* P0 = s1 address */ define
42 R0 = [P0++];
45 MNOP || R0 = [P0++] || R1 = [I0++];
61 R0 = B[P0++](Z); /* *s1 */
81 P0 += -4; /* back up to the start of the */
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| H A D | memmove.S | 21 P0 = R0; /* P0 = To address */ define
52 [P0++] = R1;
58 MNOP || [P0++] = R1 || R1 = [I0++];
60 [P0++] = R1;
70 .Lbyte2_e: B[P0++] = R1;
77 P0 = P0 + P2; define
87 .Lol_s: B[P0--] = R1;
89 .Lno_loop: B[P0]
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| H A D | strncpy.S | 31 P0 = R0 ; /* dst*/ define
37 B [P0++] = R1;
71 R0 = P0;
81 B [P0++] = R1;
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| H A D | udivsi3.S | 133 P0 = 0; define
139 IF CC P0 = R6; /* Number of values divided */
142 /* P0 is 0, 1 (NR/=2) or 2 (NR/=2, DR/=2) */
164 CC = P0 == 0; /* Check how many inputs we shifted */
167 CC = P0 == 1;
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| /arch/blackfin/mach-common/ |
| H A D | cache.S | 49 P0 = R0; define
54 \flushins [P0++];
59 2: \flushins [P0++];
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| H A D | dpmc_modes.S | 19 P0.H = hi(PLL_CTL);
20 P0.L = lo(PLL_CTL);
21 R1 = W[P0](z);
23 W[P0] = R1.L;
38 P0.H = hi(PLL_CTL);
39 P0.L = lo(PLL_CTL);
106 P0.H = hi(PLL_DIV);
107 P0.L = lo(PLL_DIV);
108 R6 = W[P0](z);
110 W[P0]
298 P0 = 0; define
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| /arch/blackfin/kernel/ |
| H A D | fixed_code.S | 26 P0 = __NR_rt_sigreturn; define
35 * Inputs: P0: memory address to use
40 R0 = [P0];
41 [P0] = R1;
48 * Inputs: P0: memory address to use
56 R0 = [P0];
59 [P0] = R2;
67 * Inputs: P0: memory address to use
73 R1 = [P0];
75 [P0]
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| /arch/hexagon/mm/ |
| H A D | strnlen_user.S | 52 P0 = cmp.eq(mod8,#0); define
55 if (P0.new) jump:t dw_loop; /* fire up the oven */
63 P0 = cmp.eq(tmp1,#0); define
64 if (P0.new) jump:nt exit_found;
70 P0 = cmp.eq(mod8,#0); define
73 if (!P0) jump alignment_loop;
84 P0 = vcmpb.eq(dbuf,dcmp); define
87 tmp1 = P0;
88 P0 = cmp.gtu(end,start); define
93 if (!P0) jum
96 P0 = cmp.eq(tmp1,#32); define
108 P0 = cmp.gt(tmp1,mod8); define
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| /arch/hexagon/kernel/ |
| H A D | vm_entry.S | 297 P0 = tstbit(R0, #HVM_VMEST_UM_SFT); define
298 if (!P0.new) jump:nt restore_all;
320 P0 = cmp.eq(R0, #0); if (!P0.new) jump:nt check_work_pending; define
381 P0 = cmp.eq(R24, #0); define
385 if P0 jump check_work_pending
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| /arch/cris/arch-v10/kernel/ |
| H A D | kgdb.c | 190 There are 16 special registers, P0-P15, where three of the unimplemented
191 registers, P0, P4 and P8, are reserved as zero-registers. A read from
297 There are 16 special registers, P0-P15, where three of the unimplemented
298 registers, P0, P4 and P8, are reserved as zero-registers. A read from
306 P0, VR, P2, P3, enumerator in enum:register_name
614 else if (regno == P0 || regno == VR || regno == P4 || regno == P8) {
650 else if (regno == P0 || regno == VR) {
653 ((char *)&(current_reg->p0) + (regno-P0) * sizeof(char)));
964 " clear.b [cris_reg+0x40] ; Clear P0\n"
1057 " clear.b [cris_reg+0x40] ; Clear P0\
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