Searched defs:P4 (Results 1 - 3 of 3) sorted by relevance
| /arch/blackfin/mach-common/ |
| H A D | dpmc_modes.S | 96 P4 = R1; define
140 R1 = P4;
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| H A D | entry.S | 50 P4 = R7; /* Store EXCAUSE */ define
59 R7 = P4;
367 P4.L = LO(IMEM_CONTROL);
368 P4.H = HI(IMEM_CONTROL);
370 R5 = [P4]; /* Control Register*/
373 [P4] = R5;
376 P4.L = LO(DMEM_CONTROL);
377 P4.H = HI(DMEM_CONTROL);
378 R5 = [P4];
381 [P4]
1154 P4 = P3 + P2; define
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| /arch/cris/arch-v10/kernel/ |
| H A D | kgdb.c | 191 registers, P0, P4 and P8, are reserved as zero-registers. A read from
298 registers, P0, P4 and P8, are reserved as zero-registers. A read from
307 P4, CCR, P6, MOF, enumerator in enum:register_name
614 else if (regno == P0 || regno == VR || regno == P4 || regno == P8) {
619 /* 16 bit register with complex offset. (P4 is read-only, P6 is not implemented,
656 else if (regno == P4 || regno == CCR) {
659 ((char *)&(current_reg->p4) + (regno-P4) * sizeof(unsigned short)));
966 " clear.w [cris_reg+0x42] ; Clear P4\n"
1059 " clear.w [cris_reg+0x42] ; Clear P4\n"
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