Searched defs:chan (Results 1 - 25 of 653) sorted by relevance

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/drivers/gpu/drm/nouveau/core/engine/mpeg/
H A Dnv31.h12 struct nv31_mpeg_chan *chan; member in struct:nv31_mpeg_priv
/drivers/dma/
H A Ddmaengine.h13 * @chan: dma channel to initialize
15 static inline void dma_cookie_init(struct dma_chan *chan) argument
17 chan->cookie = DMA_MIN_COOKIE;
18 chan->completed_cookie = DMA_MIN_COOKIE;
30 struct dma_chan *chan = tx->chan; local
33 cookie = chan->cookie + 1;
36 tx->cookie = chan->cookie = cookie;
54 tx->chan->completed_cookie = tx->cookie;
60 * @chan
67 dma_cookie_status(struct dma_chan *chan, dma_cookie_t cookie, struct dma_tx_state *state) argument
[all...]
/drivers/dma/sh/
H A Dshdma-of.c27 struct dma_chan *chan; local
36 chan = dma_request_channel(mask, shdma_chan_filter,
38 if (chan)
39 to_shdma_chan(chan)->hw_req = id;
41 return chan;
/drivers/gpu/drm/nouveau/core/engine/graph/
H A Dnv25.c47 struct nv20_graph_chan *chan; local
51 16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
52 *pobject = nv_object(chan);
56 chan->chid = nouveau_fifo_chan(parent)->chid;
58 nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24));
59 nv_wo32(chan, 0x035c, 0xffff0000);
60 nv_wo32(chan, 0x03c0, 0x0fff0000);
61 nv_wo32(chan, 0x03c4, 0x0fff0000);
62 nv_wo32(chan,
[all...]
H A Dnv2a.c23 struct nv20_graph_chan *chan; local
27 16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
28 *pobject = nv_object(chan);
32 chan->chid = nouveau_fifo_chan(parent)->chid;
34 nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24));
35 nv_wo32(chan, 0x033c, 0xffff0000);
36 nv_wo32(chan, 0x03a0, 0x0fff0000);
37 nv_wo32(chan, 0x03a4, 0x0fff0000);
38 nv_wo32(chan,
[all...]
H A Dnv34.c49 struct nv20_graph_chan *chan; local
53 16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
54 *pobject = nv_object(chan);
58 chan->chid = nouveau_fifo_chan(parent)->chid;
60 nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24));
61 nv_wo32(chan, 0x040c, 0x01000101);
62 nv_wo32(chan, 0x0420, 0x00000111);
63 nv_wo32(chan, 0x0424, 0x00000060);
64 nv_wo32(chan,
[all...]
H A Dnv35.c47 struct nv20_graph_chan *chan; local
51 16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
52 *pobject = nv_object(chan);
56 chan->chid = nouveau_fifo_chan(parent)->chid;
58 nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24));
59 nv_wo32(chan, 0x040c, 0x00000101);
60 nv_wo32(chan, 0x0420, 0x00000111);
61 nv_wo32(chan, 0x0424, 0x00000060);
62 nv_wo32(chan,
[all...]
H A Dnv30.c49 struct nv20_graph_chan *chan; local
53 16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
54 *pobject = nv_object(chan);
58 chan->chid = nouveau_fifo_chan(parent)->chid;
60 nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24));
61 nv_wo32(chan, 0x0410, 0x00000101);
62 nv_wo32(chan, 0x0424, 0x00000111);
63 nv_wo32(chan, 0x0428, 0x00000060);
64 nv_wo32(chan,
[all...]
/drivers/gpu/drm/nouveau/core/engine/software/
H A Dnvc0.c44 struct nv50_software_chan *chan = (void *)nv_engctx(object->parent); local
47 chan->vblank.offset &= 0x00ffffffffULL;
48 chan->vblank.offset |= data << 32;
50 chan->vblank.offset &= 0xff00000000ULL;
51 chan->vblank.offset |= data;
60 struct nv50_software_chan *chan = (void *)nv_engctx(object->parent); local
61 struct nv50_software_priv *priv = (void *)nv_object(chan)->engine;
108 struct nv50_software_chan *chan = local
109 container_of(notify, typeof(*chan), vblank.notify[notify->index]);
110 struct nv50_software_priv *priv = (void *)nv_object(chan)
[all...]
/drivers/gpu/drm/nouveau/
H A Dnv10_fence.c32 struct nouveau_channel *chan = fence->channel; local
33 int ret = RING_SPACE(chan, 2);
35 BEGIN_NV04(chan, 0, NV10_SUBCHAN_REF_CNT, 1);
36 OUT_RING (chan, fence->base.seqno);
37 FIRE_RING (chan);
45 struct nouveau_channel *prev, struct nouveau_channel *chan)
51 nv10_fence_read(struct nouveau_channel *chan) argument
53 return nvif_rd32(chan, 0x0048);
57 nv10_fence_context_del(struct nouveau_channel *chan) argument
59 struct nv10_fence_chan *fctx = chan
44 nv10_fence_sync(struct nouveau_fence *fence, struct nouveau_channel *prev, struct nouveau_channel *chan) argument
70 nv10_fence_context_new(struct nouveau_channel *chan) argument
[all...]
H A Dnv17_fence.c34 struct nouveau_channel *prev, struct nouveau_channel *chan)
37 struct nv10_fence_priv *priv = chan->drm->fence;
38 struct nv10_fence_chan *fctx = chan->fence;
60 if (!ret && !(ret = RING_SPACE(chan, 5))) {
61 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4);
62 OUT_RING (chan, fctx->sema.handle);
63 OUT_RING (chan, 0);
64 OUT_RING (chan, value + 1);
65 OUT_RING (chan, value + 2);
66 FIRE_RING (chan);
33 nv17_fence_sync(struct nouveau_fence *fence, struct nouveau_channel *prev, struct nouveau_channel *chan) argument
74 nv17_fence_context_new(struct nouveau_channel *chan) argument
[all...]
H A Dnv50_fence.c35 nv50_fence_context_new(struct nouveau_channel *chan) argument
37 struct drm_device *dev = chan->drm->dev;
38 struct nv10_fence_priv *priv = chan->drm->fence;
45 fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
49 nouveau_fence_context_new(chan, &fctx->base);
54 ret = nvif_object_init(chan->object, NULL, NvSema, NV_DMA_IN_MEMORY,
69 ret = nvif_object_init(chan->object, NULL, NvEvoSema0 + i,
80 nv10_fence_context_del(chan);
H A Dnvc0_fence.c32 nvc0_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence) argument
34 int ret = RING_SPACE(chan, 6);
36 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5);
37 OUT_RING (chan, upper_32_bits(virtual));
38 OUT_RING (chan, lower_32_bits(virtual));
39 OUT_RING (chan, sequence);
40 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
41 OUT_RING (chan, 0x00000000);
42 FIRE_RING (chan);
48 nvc0_fence_sync32(struct nouveau_channel *chan, u6 argument
64 nvc0_fence_context_new(struct nouveau_channel *chan) argument
[all...]
H A Dnv04_fence.c40 struct nouveau_channel *chan = fence->channel; local
41 int ret = RING_SPACE(chan, 2);
43 BEGIN_NV04(chan, NvSubSw, 0x0150, 1);
44 OUT_RING (chan, fence->base.seqno);
45 FIRE_RING (chan);
52 struct nouveau_channel *prev, struct nouveau_channel *chan)
58 nv04_fence_read(struct nouveau_channel *chan) argument
60 struct nouveau_fifo_chan *fifo = nvkm_fifo_chan(chan);;
65 nv04_fence_context_del(struct nouveau_channel *chan) argument
67 struct nv04_fence_chan *fctx = chan
51 nv04_fence_sync(struct nouveau_fence *fence, struct nouveau_channel *prev, struct nouveau_channel *chan) argument
74 nv04_fence_context_new(struct nouveau_channel *chan) argument
[all...]
/drivers/isdn/hysdn/
H A Dhysdn_sched.c32 unsigned short chan)
35 switch (chan) {
57 printk(KERN_INFO "irq message channel %d len %d unhandled \n", chan, len);
68 /* If the routine wants to send data it must fill buf, len and chan with the */
75 unsigned short volatile *len, unsigned short volatile *chan,
89 *chan = card->async_channel;
99 *chan = CHAN_ERRLOG; /* and channel */
107 *chan = CHAN_ERRLOG; /* and channel */
119 *chan = CHAN_NDIS_DATA;
132 *chan
31 hysdn_sched_rx(hysdn_card *card, unsigned char *buf, unsigned short len, unsigned short chan) argument
74 hysdn_sched_tx(hysdn_card *card, unsigned char *buf, unsigned short volatile *len, unsigned short volatile *chan, unsigned short maxlen) argument
150 hysdn_tx_cfgline(hysdn_card *card, unsigned char *line, unsigned short chan) argument
[all...]
/drivers/staging/comedi/drivers/
H A Ddac02.c82 unsigned int chan = CR_CHAN(insn->chanspec); local
90 s->readback[chan] = val;
104 outb((val << 4) & 0xf0, dev->iobase + DAC02_AO_LSB(chan));
105 outb((val >> 4) & 0xff, dev->iobase + DAC02_AO_MSB(chan));
H A Ddt2817.c47 unsigned int chan = CR_CHAN(insn->chanspec); local
52 if (chan < 8)
54 else if (chan < 16)
56 else if (chan < 24)
H A Dfl512.c64 unsigned int chan = CR_CHAN(insn->chanspec); local
68 outb(chan, dev->iobase + FL512_AI_MUX_REG);
91 unsigned int chan = CR_CHAN(insn->chanspec); local
92 unsigned int val = s->readback[chan];
99 outb(val & 0x0ff, dev->iobase + FL512_AO_DATA_REG(chan));
100 outb((val >> 8) & 0xf, dev->iobase + FL512_AO_DATA_REG(chan));
101 inb(dev->iobase + FL512_AO_TRIG_REG(chan));
103 s->readback[chan] = val;
H A Dpcmda12.c73 unsigned int chan = CR_CHAN(insn->chanspec); local
74 unsigned int val = s->readback[chan];
75 unsigned long ioreg = dev->iobase + (chan * 2);
90 s->readback[chan] = val;
/drivers/gpu/drm/gma500/
H A Dintel_i2c.c35 struct psb_intel_i2c_chan *chan = data; local
36 struct drm_device *dev = chan->drm_dev;
39 val = REG_READ(chan->reg);
45 struct psb_intel_i2c_chan *chan = data; local
46 struct drm_device *dev = chan->drm_dev;
49 val = REG_READ(chan->reg);
55 struct psb_intel_i2c_chan *chan = data; local
56 struct drm_device *dev = chan->drm_dev;
61 REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE |
69 REG_WRITE(chan
75 struct psb_intel_i2c_chan *chan = data; local
119 struct psb_intel_i2c_chan *chan; local
162 psb_intel_i2c_destroy(struct psb_intel_i2c_chan *chan) argument
[all...]
/drivers/gpu/drm/nouveau/core/engine/fifo/
H A Dnv10.c67 struct nv04_fifo_chan *chan; local
82 (1ULL << NVDEV_ENGINE_GR), &chan);
83 *pobject = nv_object(chan);
87 args->v0.chid = chan->base.chid;
89 nv_parent(chan)->object_attach = nv04_fifo_object_attach;
90 nv_parent(chan)->object_detach = nv04_fifo_object_detach;
91 nv_parent(chan)->context_attach = nv04_fifo_context_attach;
92 chan->ramfc = chan->base.chid * 32;
94 nv_wo32(priv->ramfc, chan
[all...]
/drivers/iio/imu/
H A Dadis_buffer.c27 const struct iio_chan_spec *chan; local
63 chan = indio_dev->channels;
64 for (i = 0; i < indio_dev->num_channels; i++, chan++) {
65 if (!test_bit(chan->scan_index, scan_mask))
67 if (chan->scan_type.storagebits == 32)
68 *tx++ = cpu_to_be16((chan->address + 2) << 8);
69 *tx++ = cpu_to_be16(chan->address << 8);
/drivers/isdn/pcbit/
H A Dcallbacks.c42 void cb_out_1(struct pcbit_dev *dev, struct pcbit_chan *chan, argument
60 chan->proto)) < 0)
69 chan->callref = 0;
70 chan->layer2link = 0;
71 chan->snum = 0;
72 chan->s_refnum = refnum;
84 void cb_out_2(struct pcbit_dev *dev, struct pcbit_chan *chan, argument
92 if ((len = capi_conn_active_resp(chan, &skb)) < 0)
99 chan->s_refnum = refnum;
106 ictl.arg = chan
130 cb_in_1(struct pcbit_dev *dev, struct pcbit_chan *chan, struct callb_data *cbdata) argument
190 cb_in_2(struct pcbit_dev *dev, struct pcbit_chan *chan, struct callb_data *data) argument
216 cb_in_3(struct pcbit_dev *dev, struct pcbit_chan *chan, struct callb_data *data) argument
242 cb_disc_1(struct pcbit_dev *dev, struct pcbit_chan *chan, struct callb_data *data) argument
271 cb_disc_2(struct pcbit_dev *dev, struct pcbit_chan *chan, struct callb_data *data) argument
295 cb_disc_3(struct pcbit_dev *dev, struct pcbit_chan *chan, struct callb_data *data) argument
306 cb_notdone(struct pcbit_dev *dev, struct pcbit_chan *chan, struct callb_data *data) argument
314 cb_selp_1(struct pcbit_dev *dev, struct pcbit_chan *chan, struct callb_data *data) argument
336 cb_open(struct pcbit_dev *dev, struct pcbit_chan *chan, struct callb_data *data) argument
[all...]
/drivers/staging/iio/
H A Diio_simple_dummy_events.c26 * @chan: channel for the event whose state is being queried
34 const struct iio_chan_spec *chan,
46 * @chan: channel for the event whose state is being set
56 const struct iio_chan_spec *chan,
67 switch (chan->type) {
89 * @chan: channel for the event whose value is being read
102 const struct iio_chan_spec *chan,
118 * @chan: channel for the event whose value is being set
125 const struct iio_chan_spec *chan,
33 iio_simple_dummy_read_event_config(struct iio_dev *indio_dev, const struct iio_chan_spec *chan, enum iio_event_type type, enum iio_event_direction dir) argument
55 iio_simple_dummy_write_event_config(struct iio_dev *indio_dev, const struct iio_chan_spec *chan, enum iio_event_type type, enum iio_event_direction dir, int state) argument
101 iio_simple_dummy_read_event_value(struct iio_dev *indio_dev, const struct iio_chan_spec *chan, enum iio_event_type type, enum iio_event_direction dir, enum iio_event_info info, int *val, int *val2) argument
124 iio_simple_dummy_write_event_value(struct iio_dev *indio_dev, const struct iio_chan_spec *chan, enum iio_event_type type, enum iio_event_direction dir, enum iio_event_info info, int val, int val2) argument
/drivers/staging/iio/resolver/
H A Dad2s90.c29 struct iio_chan_spec const *chan,
28 ad2s90_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long m) argument

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