/drivers/irqchip/ |
H A D | irq-dw-apb-ictl.c | 56 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; local 117 np->name, handle_level_irq, clr, 0,
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H A D | irq-moxart.c | 64 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; local 84 clr, 0, IRQ_GC_INIT_MASK_CACHE);
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H A D | irq-nvic.c | 55 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; local 81 clr, 0, IRQ_GC_INIT_MASK_CACHE);
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H A D | irq-bcm7120-l2.c | 120 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; local 175 dn->full_name, handle_level_irq, clr, 0,
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H A D | irq-brcmstb-l2.c | 116 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; local 153 np->full_name, handle_edge_irq, clr, 0, 0);
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H A D | irq-orion.c | 56 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; local 72 handle_level_irq, clr, 0, 142 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; local 159 handle_edge_irq, clr, 0, IRQ_GC_INIT_MASK_CACHE);
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H A D | irq-sirfsoc.c | 36 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; local 40 handle_level_irq, clr, set, IRQ_GC_INIT_MASK_CACHE);
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H A D | irq-sunxi-nmi.c | 127 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; local 138 handle_fasteoi_irq, clr, 0,
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H A D | irq-zevio.c | 78 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; local 107 clr, 0, IRQ_GC_INIT_MASK_CACHE);
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/drivers/net/wireless/ath/ath9k/ |
H A D | ar9003_wow.c | 112 u32 set, clr; local 161 clr = AR_WOW_LENGTH1_MASK(pattern_count); 162 REG_RMW(ah, AR_WOW_LENGTH1, set, clr); 167 clr = AR_WOW_LENGTH2_MASK(pattern_count); 168 REG_RMW(ah, AR_WOW_LENGTH2, set, clr); 245 u32 set, clr; local 267 clr = AR_WA_UNTIE_RESET_EN | AR_WA_D3_L1_DISABLE; 268 REG_RMW(ah, AR_WA, set, clr); 282 clr = AR_PMCTRL_WOW_PME_CLR; 283 REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr); [all...] |
H A D | htc_drv_init.c | 359 static u32 ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) argument 364 val &= ~clr;
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H A D | eeprom_4k.c | 1064 u32 pwrctrl, mask, clr; local 1068 clr = mask * 0x1f; 1069 REG_RMW(ah, AR_PHY_TX_PWRCTRL8, pwrctrl, clr); 1070 REG_RMW(ah, AR_PHY_TX_PWRCTRL10, pwrctrl, clr); 1071 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL12, pwrctrl, clr); 1075 clr = mask * 0x1f; 1076 REG_RMW(ah, AR_PHY_TX_PWRCTRL9, pwrctrl, clr); 1080 clr = mask * 0x1f; 1081 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL11, pwrctrl, clr); 1082 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr); [all...] |
H A D | init.c | 130 u32 set, u32 clr) 135 val &= ~clr; 142 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) argument 152 val = __ath9k_reg_rmw(sc, reg_offset, set, clr); 155 val = __ath9k_reg_rmw(sc, reg_offset, set, clr); 129 __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset, u32 set, u32 clr) argument
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/drivers/clocksource/ |
H A D | time-armada-370-xp.c | 88 static void local_timer_ctrl_clrset(u32 clr, u32 set) argument 90 writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set, 172 u32 clr = 0, set = 0; local 178 clr = TIMER0_25MHZ; 179 local_timer_ctrl_clrset(clr, set); 228 u32 clr = 0, set = 0; local 239 clr = TIMER0_25MHZ; 242 atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set); 243 local_timer_ctrl_clrset(clr, set);
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/drivers/gpio/ |
H A D | gpio-generic.c | 326 * - set/clear pair (named "set" and "clr"). 331 * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit 346 void __iomem *clr) 353 if (set && clr) { 355 bgc->reg_clr = clr; 357 } else if (set && !clr) { 408 void __iomem *clr, void __iomem *dirout, void __iomem *dirin, 427 ret = bgpio_setup_io(bgc, dat, set, clr); 497 void __iomem *clr; local 520 clr 343 bgpio_setup_io(struct bgpio_chip *bgc, void __iomem *dat, void __iomem *set, void __iomem *clr) argument 406 bgpio_init(struct bgpio_chip *bgc, struct device *dev, unsigned long sz, void __iomem *dat, void __iomem *set, void __iomem *clr, void __iomem *dirout, void __iomem *dirin, unsigned long flags) argument [all...] |
/drivers/gpu/drm/rcar-du/ |
H A D | rcar_du_crtc.c | 43 static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr) argument 48 rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr); 60 u32 clr, u32 set) 65 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, (value & ~clr) | set); 59 rcar_du_crtc_clr_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr, u32 set) argument
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/drivers/iio/dac/ |
H A D | ad5421.c | 184 unsigned int clr) 191 st->ctrl &= ~clr; 183 ad5421_update_ctrl(struct iio_dev *indio_dev, unsigned int set, unsigned int clr) argument
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H A D | ad5360.c | 260 unsigned int clr) 268 st->ctrl &= ~clr; 259 ad5360_update_ctrl(struct iio_dev *indio_dev, unsigned int set, unsigned int clr) argument
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H A D | ad5755.c | 184 unsigned int channel, unsigned int set, unsigned int clr) 190 st->ctrl[channel] &= ~clr; 183 ad5755_update_dac_ctrl(struct iio_dev *indio_dev, unsigned int channel, unsigned int set, unsigned int clr) argument
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/drivers/staging/media/omap4iss/ |
H A D | iss.h | 190 * @clr: bit mask to be cleared 194 u32 offset, u32 clr) 198 iss_reg_write(iss, res, offset, v & ~clr); 222 * @clr: bit mask to be cleared 225 * Clear the clr mask first and then set the set mask. 229 u32 offset, u32 clr, u32 set) 233 iss_reg_write(iss, res, offset, (v & ~clr) | set); 193 iss_reg_clr(struct iss_device *iss, enum iss_mem_resources res, u32 offset, u32 clr) argument 228 iss_reg_update(struct iss_device *iss, enum iss_mem_resources res, u32 offset, u32 clr, u32 set) argument
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/drivers/usb/serial/ |
H A D | ark3116.c | 460 unsigned set, unsigned clr) 479 if (clr & TIOCM_RTS) 481 if (clr & TIOCM_DTR) 483 if (clr & TIOCM_OUT1) 485 if (clr & TIOCM_OUT2) 459 ark3116_tiocmset(struct tty_struct *tty, unsigned set, unsigned clr) argument
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/drivers/gpu/drm/radeon/ |
H A D | radeon_ioc32.c | 110 drm_radeon_clear_t __user *clr; local 115 clr = compat_alloc_user_space(sizeof(*clr)); 116 if (!access_ok(VERIFY_WRITE, clr, sizeof(*clr)) 117 || __put_user(clr32.flags, &clr->flags) 118 || __put_user(clr32.clear_color, &clr->clear_color) 119 || __put_user(clr32.clear_depth, &clr->clear_depth) 120 || __put_user(clr32.color_mask, &clr->color_mask) 121 || __put_user(clr32.depth_mask, &clr [all...] |
/drivers/misc/ |
H A D | hpilo.c | 398 static inline void clear_pending_db(struct ilo_hwinfo *hw, int clr) argument 400 iowrite32(clr, &hw->mmio_vaddr[DB_OUT]);
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/drivers/video/fbdev/ |
H A D | hpfb.c | 152 u8 clr; local 154 clr = region->color & 0xff; 160 out_8(fb_regs + TC_WEN, fb_bitmask & clr); 164 out_8(fb_regs + TC_WEN, fb_bitmask & ~clr);
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/drivers/i2c/busses/ |
H A D | i2c-sh_mobile.c | 193 unsigned char set, unsigned char clr) 195 iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr); 192 iic_set_clr(struct sh_mobile_i2c_data *pd, int offs, unsigned char set, unsigned char clr) argument
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