Searched defs:control (Results 276 - 300 of 317) sorted by relevance

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/drivers/scsi/
H A Dmvumi.h449 /* The format of the page code for firmware control */
454 u16 control; member in struct:mvumi_hs_page3
H A Dhpsa.c85 /* define the PCI info for the cards we can control */
3300 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE; local
3342 control |= IOACCEL1_CONTROL_DATA_OUT;
3345 control |= IOACCEL1_CONTROL_DATA_IN;
3348 control |= IOACCEL1_CONTROL_NODATAXFER;
3357 control |= IOACCEL1_CONTROL_NODATAXFER;
3366 cp->control = control;
7630 * This is it. Register the PCI driver information for the cards we control
7707 VERIFY_OFFSET(control,
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/drivers/usb/gadget/udc/
H A Dfsl_usb2_udc.h105 u32 control; /* General Purpose Control Register */ member in struct:usb_sys_interface
150 /* bit 23-16 are interrupt threshold control */
224 /* bit 15-14 are port indicator control */
231 /* bit 19-16 are port test control */
359 /* control Register Bit Masks */
/drivers/acpi/acpica/
H A Daclocal.h601 * states are created when there are nested control methods executing.
647 struct acpi_control_state control; member in union:acpi_generic_state
797 * Parse state - one state per parser invocation and each control
853 /* For control registers, both ignored and reserved bits must be preserved */
856 * For PM1 control, the SCI enable bit (bit 0, SCI_EN) is defined by the
/drivers/block/
H A Dnvme-scsi.c2019 u16 control = 0; local
2024 control |= NVME_RW_FUA;
2026 return control;
2045 u16 control; local
2084 control = nvme_trans_io_get_control(ns, cdb_info);
2085 c.rw.control = cpu_to_le16(control);
/drivers/gpu/drm/radeon/
H A Dcik.c3977 u32 size_in_bytes, cur_size_in_bytes, control; local
4004 control = 0;
4006 control |= PACKET3_DMA_DATA_CP_SYNC;
4008 radeon_ring_write(ring, control);
4049 u32 header, control = INDIRECT_BUFFER_VALID; local
4077 control |= ib->length_dw |
4087 radeon_ring_write(ring, control);
4965 PRIV_STATE | KMD_QUEUE; /* assuming kernel queue control */
5717 /* Setup TLB control */
5839 /* Setup TLB control */
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/drivers/infiniband/hw/qib/
H A Dqib.h432 /* sampling counters (these are actually control registers) */
636 /* LID mask control */
669 /* Shadow copy of the congestion control table */
672 /* Shadow copy of the congestion control entries */
675 /* List of congestion control table entries */
681 /* Maximum number of congestion control entries that the agent expects
686 /* Total number of congestion control table entries */
692 /* maximum congestion control table index */
695 /* CA's max number of 64 entry units in the congestion control table */
1019 /* shadow the control registe
1020 u32 control; member in struct:qib_devdata
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H A Dqib_iba7322.c454 #define PBC_7322_VL15_SEND_CTRL (1ULL << 31) /* control version of same */
2072 qib_write_kreg(dd, kr_control, dd->control);
2315 * in units of 64 bytes (same as IB flow control credit unit).
2414 * Flow control is sent this often, even if no changes in
2421 /* IB credit flow control. */
3722 val = dd->control | QLOGIC_IB_C_RESET;
5266 u32 pnum, control, len; local
5271 control = qib_7322_setpbc_control(ppd, len, 0, 15);
5272 pbc = ((u64) control << 32) | len;
6236 dd->control
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/drivers/media/platform/exynos4-is/
H A Dfimc-is-param.h674 struct param_control control; member in struct:sensor_param
680 struct param_control control; member in struct:buffer_param
686 struct param_control control; member in struct:isp_param
704 struct param_control control; member in struct:drc_param
711 struct param_control control; member in struct:scalerc_param
721 struct param_control control; member in struct:odc_param
727 struct param_control control; member in struct:dis_param
733 struct param_control control; member in struct:tdnr_param
741 struct param_control control; member in struct:scalerp_param
753 struct param_control control; member in struct:fd_param
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/drivers/net/usb/
H A Dr8152.c569 struct mutex control; /* use for hw setting */ member in struct:r8152
981 mutex_lock(&tp->control);
989 mutex_unlock(&tp->control);
2150 mutex_lock(&tp->control);
2159 mutex_unlock(&tp->control);
2862 if (!mutex_trylock(&tp->control)) {
2882 mutex_unlock(&tp->control);
2906 mutex_lock(&tp->control);
2938 mutex_unlock(&tp->control);
2960 mutex_lock(&tp->control);
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/drivers/net/wireless/iwlegacy/
H A D4965-mac.c501 * if the radio's automatic gain control (AGC) is working right.
1588 rate_idx = info->control.rates[0].idx;
1589 if ((info->control.rates[0].flags & IEEE80211_TX_RC_MCS) || rate_idx < 0
1617 struct ieee80211_key_conf *keyconf = info->control.hw_key;
1808 if (info->control.hw_key)
2732 IL_ERR("BUG_ON idx doesn't match seq control"
2893 * translate ucode response to mac80211 tx status control values
5875 struct ieee80211_tx_control *control,
5885 if (il4965_tx_skb(il, control->sta, skb))
6827 pr_err("Unable to register rate control algorith
5874 il4965_mac_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control, struct sk_buff *skb) argument
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H A Dcommands.h621 /* pass control & management to host */
1252 * uCode handles all timing and protocol related to control frames
1310 /* 1: uCode overrides sequence control field in MAC header.
1311 * 0: Driver provides sequence control field in MAC header.
1341 * TX command security control
1539 * control line, and then waiting for the TX Abort command response. This
1542 * control line. Receiving is still allowed in this case.
1930 * (attempted - success), and control the size of the win (attempted).
2062 __le16 control; /* not used */ member in struct:il_link_quality_cmd
2434 * background. The max_out_time and suspend_time control th
3219 __le16 control; /* always use "1" */ member in struct:il_sensitivity_cmd
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/drivers/scsi/aic7xxx/
H A Daic79xx.h491 /*18*/ uint8_t control; /* See SCB_CONTROL in aic79xx.reg for details */ member in struct:hardware_scb
871 #define CFSTPWLEVEL 0x0040 /* Termination level control */
H A Daic79xx_core.c444 scb->hscb->task_attribute = scb->hscb->control & SCB_TAG_TYPE;
1966 scb->hscb->control &= ~(TAG_ENB|SCB_TAG_TYPE);
1967 scb->hscb->control |= MK_MESSAGE;
1968 ahd_outb(ahd, SCB_CONTROL, scb->hscb->control);
3291 if ((scb->hscb->control & TAG_ENB) != 0)
3604 printk("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
3606 hscb->control,
4251 pending_scb->hscb->control &= ~MK_MESSAGE;
4285 u_int control; local
4289 control
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H A Daic7xxx.h462 /*24*/ uint8_t control; /* See SCB_CONTROL in aic7xxx.reg for details */ member in struct:hardware_scb
796 #define CFSTPWLEVEL 0x0010 /* Termination level control */
1027 * Cached copy of the sequencer control register.
/drivers/scsi/qla4xxx/
H A Dql4_def.h488 uint8_t control; member in struct:ipaddress_config
/drivers/staging/rtl8188eu/include/
H A Dwifi.h81 /* below is for control frame */
625 unsigned short control; member in struct:rtw_ieee80211_bar
629 /* 802.11 BAR control masks */
/drivers/tty/serial/
H A Dioc4_serial.c190 /* Bitmasks for serial TX control byte */
194 #define IOC4_TXCB_MCR 0x80 /* Data<7:0> to modem control reg */
203 #define IOC4_SSCR_HFC_EN 0x00020000 /* Hardware flow control enabled */
599 char sc[4]; /* status/control */
739 * get_ioc4_port - given a uart port, return the control structure
746 struct ioc4_control *control = idd->idd_serial_data; local
750 if (control) {
753 port = control->ic_port[port_num].icp_port;
860 /* Set line control to 8 bits no parity */
870 /* Clear modem control registe
1058 struct ioc4_control* control = idd->idd_serial_data; local
2539 struct ioc4_control *control; local
2641 struct ioc4_control *control; local
2710 struct ioc4_control *control = idd->idd_serial_data; local
2775 struct ioc4_control *control; local
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/drivers/atm/
H A Diphase.h23 in terms of PHY type, the size of control memory and the size of
32 Add the flow control logic to the driver to allow rate-limit VC.
33 Add 4K VC support to the board with 512K control memory.
196 u_short control; member in struct:cpcs_trailer
346 /*------------ Bus interface control registers -----------------*/
395 /*--------------- Segmentation control registers -----------------*/
480 /*----------------- Reassembly control registers ---------------------*/
556 /*----------------- Front End registers/ DMA control --------------*/
991 u32 __iomem *dma; /* Base pointer into DMA control registers. */
1065 MB25_MASTER_CTRL = 0x00, /* Master control */
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/drivers/gpu/drm/i915/
H A Dintel_display.c2482 /* pipesrc and dspsize control the size that is scaled from,
4422 if (!crtc->config.gmch_pfit.control)
4433 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4914 if (!crtc->config.gmch_pfit.control)
4945 * Vblank time updates from the shadow to live plane control register
6300 pipe_config->gmch_pfit.control = tmp;
6556 * enabling. This is only under driver's control after
10300 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10301 pipe_config->gmch_pfit.control,
10786 PIPE_CONF_CHECK_I(gmch_pfit.control);
13612 u32 control; member in struct:intel_display_error_state::intel_cursor_error_state
13625 u32 control; member in struct:intel_display_error_state::intel_plane_error_state
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/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_main.c13078 u16 control = 0; local
13097 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control);
13099 index = control & PCI_MSIX_FLAGS_QSIZE;
/drivers/net/wireless/ipw2x00/
H A Dipw2200.c1545 IPW_DEBUG_LED("Disabling LED control.\n");
1549 IPW_DEBUG_LED("Enabling LED control.\n");
1616 * Add a device attribute to view/control the delay between eeprom
2790 u32 control = 0; local
2795 control = DMA_CONTROL_SMALL_CB_CONST_VALUE | DMA_CB_STOP_AND_ABORT;
2796 ipw_write_reg32(priv, IPW_DMA_I_DMA_CONTROL, control);
2820 u32 control = 0; local
2835 control = DMA_CONTROL_SMALL_CB_CONST_VALUE | DMA_CB_START;
2836 ipw_write_reg32(priv, IPW_DMA_I_DMA_CONTROL, control);
2903 u32 control local
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/drivers/net/wireless/iwlwifi/mvm/
H A Dfw-api.h278 * Calibration control struct.
845 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq
1658 * enum iwl_scd_control - scheduler config command control flags
1692 * @control: command control flags
1710 u8 control; member in struct:iwl_scd_txq_cfg_cmd
/drivers/net/wireless/
H A Dmwl8k.c899 key_conf = tx_info->control.hw_key;
1736 /* Rate control is happening in the firmware.
1926 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
1934 /* Setup firmware control bit fields for each frame type. */
2758 __le16 control; member in struct:mwl8k_cmd_radio_control
2779 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
4672 struct ieee80211_tx_control *control,
4685 mwl8k_txq_xmit(hw, index, control->sta, skb);
5219 * AP firmware doesn't allow fine-grained control over
5458 * because we do our own rate control
4671 mwl8k_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control, struct sk_buff *skb) argument
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/drivers/scsi/esas2r/
H A Datioctl.h129 * CSMI control codes
630 struct atto_csmi_pc_ctrl control[1]; member in struct:atto_csmi_phy_ctrl

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