/arch/mips/pci/ |
H A D | ops-mace.c | 44 u32 control = mace->pci.control; local 47 mace->pci.control = control & ~MACEPCI_CONTROL_MAR_INT; 62 mace->pci.control = control;
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H A D | msi-octeon.c | 52 * programming the MSI control bits [6:4] before calling 63 u16 control; local 76 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); 84 configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4; 87 request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1; 176 control &= ~PCI_MSI_FLAGS_QSIZE; 177 control |= request_private_bits << 4; 178 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
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/arch/um/drivers/ |
H A D | daemon.h | 20 int control; member in struct:daemon_data
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/arch/mips/include/asm/ |
H A D | m48t37.h | 21 volatile u8 control; member in struct:m48t37_rtc
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/arch/arm/mach-ixp4xx/include/mach/ |
H A D | ixp46x_ts.h | 39 u32 control; /* 0x00 Time Sync Control Register */ member in struct:ixp46x_ts_regs
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/arch/mips/include/asm/mach-rc32434/ |
H A D | dma.h | 23 u32 control; /* Control. use DMAD_* */ member in struct:dma_desc 25 u32 devcs; /* Device control and status. */
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/arch/mips/oprofile/ |
H A D | op_model_mipsxx.c | 142 unsigned int control[4]; member in struct:mipsxx_register_config 153 /* Compute the performance counter control word. */ 155 reg.control[i] = 0; 161 reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) | 164 reg.control[i] |= M_PERFCTL_KERNEL; 166 reg.control[i] |= M_PERFCTL_USER; 168 reg.control[i] |= M_PERFCTL_EXL; 170 reg.control[i] |= M_PERFCTL_COUNT_ALL_THREADS; 210 w_c0_perfctrl3(WHAT | reg.control[3]); 212 w_c0_perfctrl2(WHAT | reg.control[ 243 unsigned int control; local [all...] |
/arch/powerpc/boot/ |
H A D | mv64x60_i2c.c | 75 static int mv64x60_i2c_control(int control, int status) argument 77 out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff); 81 static int mv64x60_i2c_read_byte(int control, int status) argument 83 out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff); 89 static int mv64x60_i2c_write_byte(int data, int control, int status) argument 92 out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff); 101 int control; local 118 control = MV64x60_I2C_CONTROL_START | MV64x60_I2C_CONTROL_TWSIEN; 120 if (mv64x60_i2c_control(control, status) < 0) 125 control [all...] |
/arch/powerpc/include/asm/ |
H A D | dbdma.h | 12 * DBDMA control/status registers. All little-endian. 15 unsigned int control; /* lets you change bits in status */ member in struct:dbdma_regs 31 /* Bits in control and status registers */ 65 #define KEY_STREAM1 0x100 /* control/status stream */ 72 /* Interrupt control values in command field */ 78 /* Branch control values in command field */ 84 /* Wait control values in command field */ 96 out_le32(&((regs)->control), (RUN|FLUSH)<<16); \ 102 out_le32(&((regs)->control), (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16);\
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/arch/sparc/mm/ |
H A D | iommu.c | 61 unsigned long control; local 78 control = sbus_readl(&iommu->regs->control); 79 impl = (control & IOMMU_CTRL_IMPL) >> 28; 80 vers = (control & IOMMU_CTRL_VERS) >> 24; 81 control &= ~(IOMMU_CTRL_RNGE); 82 control |= (IOMMU_RNGE_256MB | IOMMU_CTRL_ENAB); 83 sbus_writel(control, &iommu->regs->control);
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/arch/tile/kernel/ |
H A D | single_step.c | 419 /* two wide, check for control flow */ 746 unsigned long control = __insn_mfspr(SPR_SINGLE_STEP_CONTROL_K); local 752 (!(control & SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK))) { 754 control |= SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK; 755 control |= SPR_SINGLE_STEP_CONTROL_1__INHIBIT_MASK; 756 __insn_mtspr(SPR_SINGLE_STEP_CONTROL_K, control); 763 * Called from need_singlestep. Set up the control registers and the enable 770 unsigned long control = __insn_mfspr(SPR_SINGLE_STEP_CONTROL_K); local 773 control |= SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK; 774 control | [all...] |
/arch/arm/mach-davinci/ |
H A D | board-dm644x-evm.c | 738 unsigned int control; local 744 control = phy_read(phydev, 26); 745 phy_write(phydev, 26, (control | 0x800));
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/arch/s390/include/asm/ |
H A D | ptrace.h | 89 unsigned long control; /* PER control bits */ member in struct:per_regs 107 unsigned long cr9; /* PER control bits */
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/arch/sparc/include/asm/ |
H A D | iommu_32.h | 23 volatile unsigned long control; /* IOMMU control */ member in struct:iommu_regs
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/arch/blackfin/include/asm/ |
H A D | bfin_ppi.h | 25 __BFP(control); 44 u32 control; member in struct:bfin_eppi_regs
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/arch/ia64/kernel/ |
H A D | palinfo.c | 518 static void feature_set_info(struct seq_file *m, u64 avail, u64 status, u64 control, argument 525 for(i=0; i < 64; i++, avail >>=1, status >>=1, control >>=1) { 527 if (!(control)) /* No remaining bits set */ 537 avail & 0x1 ? (control & 0x1 ? 545 avail & 0x1 ? (control & 0x1 ? 553 u64 avail=1, status=1, control=1, feature_set=0; local 557 ret = ia64_pal_proc_get_features(&avail, &status, &control, 567 feature_set_info(m, avail, status, control, feature_set); 604 u64 avail, status, control; local 613 control [all...] |
/arch/mips/include/asm/ip32/ |
H A D | crime.h | 31 volatile unsigned long control; member in struct:sgi_crime
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H A D | mace.h | 49 volatile unsigned int control; member in struct:mace_pci 135 volatile unsigned long control; member in struct:mace_audio 136 volatile unsigned long codec_control; /* codec status control */ 140 volatile unsigned long control; /* channel control */ member in struct:mace_audio::__anon1970 240 volatile unsigned long control; member in struct:mace_ps2port 259 volatile unsigned long control; member in struct:mace_i2c
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/arch/sparc/kernel/ |
H A D | pci_fire.c | 32 u64 control; local 47 /* We use the main control/status register of FIRE as the write 64 control = upa_readq(iommu->iommu_control); 65 control |= (0x00000400 /* TSB cache snoop enable */ | 69 upa_writeq(control, iommu->iommu_control);
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H A D | pci_psycho.c | 426 u64 control; local 457 * It is possible to control if PBM will be rerun on 464 control = upa_readq(pbm->stc.strbuf_control); 465 control |= PSYCHO_STRBUF_CTRL_ENAB; 466 control &= ~(PSYCHO_STRBUF_CTRL_LENAB | PSYCHO_STRBUF_CTRL_LPTR); 468 control &= ~(PSYCHO_STRBUF_CTRL_RRDIS); 471 control |= PSYCHO_STRBUF_CTRL_RRDIS; 474 upa_writeq(control, pbm->stc.strbuf_control);
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H A D | psycho_common.c | 37 u64 control; local 57 control = upa_readq(strbuf->strbuf_control); 58 upa_writeq(control | PSYCHO_STRBUF_CTRL_DENAB, strbuf->strbuf_control); 74 upa_writeq(control, strbuf->strbuf_control); 205 u64 control, iommu_tag[16], iommu_data[16]; local 210 control = upa_readq(iommu->iommu_control); 211 if (control & PSYCHO_IOMMU_CTRL_XLTEERR) { 214 control &= ~PSYCHO_IOMMU_CTRL_XLTEERR; 215 upa_writeq(control, iommu->iommu_control); 217 switch ((control 403 u64 control; local [all...] |
H A D | sbus.c | 34 #define IOMMU_CONTROL (0x2400UL - 0x2400UL) /* IOMMU control register */ 497 u64 control; local 532 control = upa_readq(iommu->write_complete_reg); 533 control |= 0x100UL; /* SBUS Error Interrupt Enable */ 534 upa_writeq(control, iommu->write_complete_reg); 546 u64 control; local 551 "control registers.\n"); 586 /* The SYSIO SBUS control register is used for dummy reads 599 control = upa_readq(iommu->iommu_control); 600 control [all...] |
/arch/avr32/mach-at32ap/ |
H A D | at32ap700x.c | 115 static unsigned long pll_get_rate(struct clk *clk, unsigned long control) argument 119 div = PM_BFEXT(PLLDIV, control) + 1; 120 mul = PM_BFEXT(PLLMUL, control) + 1; 196 u32 control; local 198 control = pm_readl(PLL0); 200 return pll_get_rate(clk, control); 240 u32 control; local 242 control = pm_readl(PLL1); 244 return pll_get_rate(clk, control); 371 u32 control; local 515 u32 control; local 527 u32 control; local 539 u32 control; local 565 u32 control; local 592 u32 control; local [all...] |
/arch/ia64/kvm/ |
H A D | kvm-ia64.c | 1606 long avail = 1, status = 1, control = 1; local 1609 ret = ia64_pal_proc_get_features(&avail, &status, &control, 0);
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/arch/x86/include/asm/ |
H A D | svm.h | 184 struct vmcb_control_area control; member in struct:vmcb
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