1/* 2 * TI DaVinci EVM board support 3 * 4 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> 5 * 6 * 2007 (c) MontaVista Software, Inc. This file is licensed under 7 * the terms of the GNU General Public License version 2. This program 8 * is licensed "as is" without any warranty of any kind, whether express 9 * or implied. 10 */ 11#include <linux/kernel.h> 12#include <linux/init.h> 13#include <linux/dma-mapping.h> 14#include <linux/platform_device.h> 15#include <linux/gpio.h> 16#include <linux/i2c.h> 17#include <linux/i2c/pcf857x.h> 18#include <linux/platform_data/at24.h> 19#include <linux/mtd/mtd.h> 20#include <linux/mtd/nand.h> 21#include <linux/mtd/partitions.h> 22#include <linux/mtd/physmap.h> 23#include <linux/phy.h> 24#include <linux/clk.h> 25#include <linux/videodev2.h> 26#include <linux/v4l2-dv-timings.h> 27#include <linux/export.h> 28 29#include <media/tvp514x.h> 30 31#include <asm/mach-types.h> 32#include <asm/mach/arch.h> 33 34#include <mach/common.h> 35#include <linux/platform_data/i2c-davinci.h> 36#include <mach/serial.h> 37#include <mach/mux.h> 38#include <linux/platform_data/mtd-davinci.h> 39#include <linux/platform_data/mmc-davinci.h> 40#include <linux/platform_data/usb-davinci.h> 41#include <linux/platform_data/mtd-davinci-aemif.h> 42 43#include "davinci.h" 44 45#define DM644X_EVM_PHY_ID "davinci_mdio-0:01" 46#define LXT971_PHY_ID (0x001378e2) 47#define LXT971_PHY_MASK (0xfffffff0) 48 49static struct mtd_partition davinci_evm_norflash_partitions[] = { 50 /* bootloader (UBL, U-Boot, etc) in first 5 sectors */ 51 { 52 .name = "bootloader", 53 .offset = 0, 54 .size = 5 * SZ_64K, 55 .mask_flags = MTD_WRITEABLE, /* force read-only */ 56 }, 57 /* bootloader params in the next 1 sectors */ 58 { 59 .name = "params", 60 .offset = MTDPART_OFS_APPEND, 61 .size = SZ_64K, 62 .mask_flags = 0, 63 }, 64 /* kernel */ 65 { 66 .name = "kernel", 67 .offset = MTDPART_OFS_APPEND, 68 .size = SZ_2M, 69 .mask_flags = 0 70 }, 71 /* file system */ 72 { 73 .name = "filesystem", 74 .offset = MTDPART_OFS_APPEND, 75 .size = MTDPART_SIZ_FULL, 76 .mask_flags = 0 77 } 78}; 79 80static struct physmap_flash_data davinci_evm_norflash_data = { 81 .width = 2, 82 .parts = davinci_evm_norflash_partitions, 83 .nr_parts = ARRAY_SIZE(davinci_evm_norflash_partitions), 84}; 85 86/* NOTE: CFI probe will correctly detect flash part as 32M, but EMIF 87 * limits addresses to 16M, so using addresses past 16M will wrap */ 88static struct resource davinci_evm_norflash_resource = { 89 .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE, 90 .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1, 91 .flags = IORESOURCE_MEM, 92}; 93 94static struct platform_device davinci_evm_norflash_device = { 95 .name = "physmap-flash", 96 .id = 0, 97 .dev = { 98 .platform_data = &davinci_evm_norflash_data, 99 }, 100 .num_resources = 1, 101 .resource = &davinci_evm_norflash_resource, 102}; 103 104/* DM644x EVM includes a 64 MByte small-page NAND flash (16K blocks). 105 * It may used instead of the (default) NOR chip to boot, using TI's 106 * tools to install the secondary boot loader (UBL) and U-Boot. 107 */ 108static struct mtd_partition davinci_evm_nandflash_partition[] = { 109 /* Bootloader layout depends on whose u-boot is installed, but we 110 * can hide all the details. 111 * - block 0 for u-boot environment ... in mainline u-boot 112 * - block 1 for UBL (plus up to four backup copies in blocks 2..5) 113 * - blocks 6...? for u-boot 114 * - blocks 16..23 for u-boot environment ... in TI's u-boot 115 */ 116 { 117 .name = "bootloader", 118 .offset = 0, 119 .size = SZ_256K + SZ_128K, 120 .mask_flags = MTD_WRITEABLE, /* force read-only */ 121 }, 122 /* Kernel */ 123 { 124 .name = "kernel", 125 .offset = MTDPART_OFS_APPEND, 126 .size = SZ_4M, 127 .mask_flags = 0, 128 }, 129 /* File system (older GIT kernels started this on the 5MB mark) */ 130 { 131 .name = "filesystem", 132 .offset = MTDPART_OFS_APPEND, 133 .size = MTDPART_SIZ_FULL, 134 .mask_flags = 0, 135 } 136 /* A few blocks at end hold a flash BBT ... created by TI's CCS 137 * using flashwriter_nand.out, but ignored by TI's versions of 138 * Linux and u-boot. We boot faster by using them. 139 */ 140}; 141 142static struct davinci_aemif_timing davinci_evm_nandflash_timing = { 143 .wsetup = 20, 144 .wstrobe = 40, 145 .whold = 20, 146 .rsetup = 10, 147 .rstrobe = 40, 148 .rhold = 10, 149 .ta = 40, 150}; 151 152static struct davinci_nand_pdata davinci_evm_nandflash_data = { 153 .parts = davinci_evm_nandflash_partition, 154 .nr_parts = ARRAY_SIZE(davinci_evm_nandflash_partition), 155 .ecc_mode = NAND_ECC_HW, 156 .ecc_bits = 1, 157 .bbt_options = NAND_BBT_USE_FLASH, 158 .timing = &davinci_evm_nandflash_timing, 159}; 160 161static struct resource davinci_evm_nandflash_resource[] = { 162 { 163 .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE, 164 .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1, 165 .flags = IORESOURCE_MEM, 166 }, { 167 .start = DM644X_ASYNC_EMIF_CONTROL_BASE, 168 .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, 169 .flags = IORESOURCE_MEM, 170 }, 171}; 172 173static struct platform_device davinci_evm_nandflash_device = { 174 .name = "davinci_nand", 175 .id = 0, 176 .dev = { 177 .platform_data = &davinci_evm_nandflash_data, 178 }, 179 .num_resources = ARRAY_SIZE(davinci_evm_nandflash_resource), 180 .resource = davinci_evm_nandflash_resource, 181}; 182 183static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32); 184 185static struct platform_device davinci_fb_device = { 186 .name = "davincifb", 187 .id = -1, 188 .dev = { 189 .dma_mask = &davinci_fb_dma_mask, 190 .coherent_dma_mask = DMA_BIT_MASK(32), 191 }, 192 .num_resources = 0, 193}; 194 195static struct tvp514x_platform_data dm644xevm_tvp5146_pdata = { 196 .clk_polarity = 0, 197 .hs_polarity = 1, 198 .vs_polarity = 1 199}; 200 201#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) 202/* Inputs available at the TVP5146 */ 203static struct v4l2_input dm644xevm_tvp5146_inputs[] = { 204 { 205 .index = 0, 206 .name = "Composite", 207 .type = V4L2_INPUT_TYPE_CAMERA, 208 .std = TVP514X_STD_ALL, 209 }, 210 { 211 .index = 1, 212 .name = "S-Video", 213 .type = V4L2_INPUT_TYPE_CAMERA, 214 .std = TVP514X_STD_ALL, 215 }, 216}; 217 218/* 219 * this is the route info for connecting each input to decoder 220 * ouput that goes to vpfe. There is a one to one correspondence 221 * with tvp5146_inputs 222 */ 223static struct vpfe_route dm644xevm_tvp5146_routes[] = { 224 { 225 .input = INPUT_CVBS_VI2B, 226 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, 227 }, 228 { 229 .input = INPUT_SVIDEO_VI2C_VI1C, 230 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, 231 }, 232}; 233 234static struct vpfe_subdev_info dm644xevm_vpfe_sub_devs[] = { 235 { 236 .name = "tvp5146", 237 .grp_id = 0, 238 .num_inputs = ARRAY_SIZE(dm644xevm_tvp5146_inputs), 239 .inputs = dm644xevm_tvp5146_inputs, 240 .routes = dm644xevm_tvp5146_routes, 241 .can_route = 1, 242 .ccdc_if_params = { 243 .if_type = VPFE_BT656, 244 .hdpol = VPFE_PINPOL_POSITIVE, 245 .vdpol = VPFE_PINPOL_POSITIVE, 246 }, 247 .board_info = { 248 I2C_BOARD_INFO("tvp5146", 0x5d), 249 .platform_data = &dm644xevm_tvp5146_pdata, 250 }, 251 }, 252}; 253 254static struct vpfe_config dm644xevm_capture_cfg = { 255 .num_subdevs = ARRAY_SIZE(dm644xevm_vpfe_sub_devs), 256 .i2c_adapter_id = 1, 257 .sub_devs = dm644xevm_vpfe_sub_devs, 258 .card_name = "DM6446 EVM", 259 .ccdc = "DM6446 CCDC", 260}; 261 262static struct platform_device rtc_dev = { 263 .name = "rtc_davinci_evm", 264 .id = -1, 265}; 266 267static struct snd_platform_data dm644x_evm_snd_data; 268 269/*----------------------------------------------------------------------*/ 270 271/* 272 * I2C GPIO expanders 273 */ 274 275#define PCF_Uxx_BASE(x) (DAVINCI_N_GPIO + ((x) * 8)) 276 277 278/* U2 -- LEDs */ 279 280static struct gpio_led evm_leds[] = { 281 { .name = "DS8", .active_low = 1, 282 .default_trigger = "heartbeat", }, 283 { .name = "DS7", .active_low = 1, }, 284 { .name = "DS6", .active_low = 1, }, 285 { .name = "DS5", .active_low = 1, }, 286 { .name = "DS4", .active_low = 1, }, 287 { .name = "DS3", .active_low = 1, }, 288 { .name = "DS2", .active_low = 1, 289 .default_trigger = "mmc0", }, 290 { .name = "DS1", .active_low = 1, 291 .default_trigger = "ide-disk", }, 292}; 293 294static const struct gpio_led_platform_data evm_led_data = { 295 .num_leds = ARRAY_SIZE(evm_leds), 296 .leds = evm_leds, 297}; 298 299static struct platform_device *evm_led_dev; 300 301static int 302evm_led_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c) 303{ 304 struct gpio_led *leds = evm_leds; 305 int status; 306 307 while (ngpio--) { 308 leds->gpio = gpio++; 309 leds++; 310 } 311 312 /* what an extremely annoying way to be forced to handle 313 * device unregistration ... 314 */ 315 evm_led_dev = platform_device_alloc("leds-gpio", 0); 316 platform_device_add_data(evm_led_dev, 317 &evm_led_data, sizeof evm_led_data); 318 319 evm_led_dev->dev.parent = &client->dev; 320 status = platform_device_add(evm_led_dev); 321 if (status < 0) { 322 platform_device_put(evm_led_dev); 323 evm_led_dev = NULL; 324 } 325 return status; 326} 327 328static int 329evm_led_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c) 330{ 331 if (evm_led_dev) { 332 platform_device_unregister(evm_led_dev); 333 evm_led_dev = NULL; 334 } 335 return 0; 336} 337 338static struct pcf857x_platform_data pcf_data_u2 = { 339 .gpio_base = PCF_Uxx_BASE(0), 340 .setup = evm_led_setup, 341 .teardown = evm_led_teardown, 342}; 343 344 345/* U18 - A/V clock generator and user switch */ 346 347static int sw_gpio; 348 349static ssize_t 350sw_show(struct device *d, struct device_attribute *a, char *buf) 351{ 352 char *s = gpio_get_value_cansleep(sw_gpio) ? "on\n" : "off\n"; 353 354 strcpy(buf, s); 355 return strlen(s); 356} 357 358static DEVICE_ATTR(user_sw, S_IRUGO, sw_show, NULL); 359 360static int 361evm_u18_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c) 362{ 363 int status; 364 365 /* export dip switch option */ 366 sw_gpio = gpio + 7; 367 status = gpio_request(sw_gpio, "user_sw"); 368 if (status == 0) 369 status = gpio_direction_input(sw_gpio); 370 if (status == 0) 371 status = device_create_file(&client->dev, &dev_attr_user_sw); 372 else 373 gpio_free(sw_gpio); 374 if (status != 0) 375 sw_gpio = -EINVAL; 376 377 /* audio PLL: 48 kHz (vs 44.1 or 32), single rate (vs double) */ 378 gpio_request(gpio + 3, "pll_fs2"); 379 gpio_direction_output(gpio + 3, 0); 380 381 gpio_request(gpio + 2, "pll_fs1"); 382 gpio_direction_output(gpio + 2, 0); 383 384 gpio_request(gpio + 1, "pll_sr"); 385 gpio_direction_output(gpio + 1, 0); 386 387 return 0; 388} 389 390static int 391evm_u18_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c) 392{ 393 gpio_free(gpio + 1); 394 gpio_free(gpio + 2); 395 gpio_free(gpio + 3); 396 397 if (sw_gpio > 0) { 398 device_remove_file(&client->dev, &dev_attr_user_sw); 399 gpio_free(sw_gpio); 400 } 401 return 0; 402} 403 404static struct pcf857x_platform_data pcf_data_u18 = { 405 .gpio_base = PCF_Uxx_BASE(1), 406 .n_latch = (1 << 3) | (1 << 2) | (1 << 1), 407 .setup = evm_u18_setup, 408 .teardown = evm_u18_teardown, 409}; 410 411 412/* U35 - various I/O signals used to manage USB, CF, ATA, etc */ 413 414static int 415evm_u35_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c) 416{ 417 /* p0 = nDRV_VBUS (initial: don't supply it) */ 418 gpio_request(gpio + 0, "nDRV_VBUS"); 419 gpio_direction_output(gpio + 0, 1); 420 421 /* p1 = VDDIMX_EN */ 422 gpio_request(gpio + 1, "VDDIMX_EN"); 423 gpio_direction_output(gpio + 1, 1); 424 425 /* p2 = VLYNQ_EN */ 426 gpio_request(gpio + 2, "VLYNQ_EN"); 427 gpio_direction_output(gpio + 2, 1); 428 429 /* p3 = n3V3_CF_RESET (initial: stay in reset) */ 430 gpio_request(gpio + 3, "nCF_RESET"); 431 gpio_direction_output(gpio + 3, 0); 432 433 /* (p4 unused) */ 434 435 /* p5 = 1V8_WLAN_RESET (initial: stay in reset) */ 436 gpio_request(gpio + 5, "WLAN_RESET"); 437 gpio_direction_output(gpio + 5, 1); 438 439 /* p6 = nATA_SEL (initial: select) */ 440 gpio_request(gpio + 6, "nATA_SEL"); 441 gpio_direction_output(gpio + 6, 0); 442 443 /* p7 = nCF_SEL (initial: deselect) */ 444 gpio_request(gpio + 7, "nCF_SEL"); 445 gpio_direction_output(gpio + 7, 1); 446 447 return 0; 448} 449 450static int 451evm_u35_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c) 452{ 453 gpio_free(gpio + 7); 454 gpio_free(gpio + 6); 455 gpio_free(gpio + 5); 456 gpio_free(gpio + 3); 457 gpio_free(gpio + 2); 458 gpio_free(gpio + 1); 459 gpio_free(gpio + 0); 460 return 0; 461} 462 463static struct pcf857x_platform_data pcf_data_u35 = { 464 .gpio_base = PCF_Uxx_BASE(2), 465 .setup = evm_u35_setup, 466 .teardown = evm_u35_teardown, 467}; 468 469/*----------------------------------------------------------------------*/ 470 471/* Most of this EEPROM is unused, but U-Boot uses some data: 472 * - 0x7f00, 6 bytes Ethernet Address 473 * - 0x0039, 1 byte NTSC vs PAL (bit 0x80 == PAL) 474 * - ... newer boards may have more 475 */ 476 477static struct at24_platform_data eeprom_info = { 478 .byte_len = (256*1024) / 8, 479 .page_size = 64, 480 .flags = AT24_FLAG_ADDR16, 481 .setup = davinci_get_mac_addr, 482 .context = (void *)0x7f00, 483}; 484 485/* 486 * MSP430 supports RTC, card detection, input from IR remote, and 487 * a bit more. It triggers interrupts on GPIO(7) from pressing 488 * buttons on the IR remote, and for card detect switches. 489 */ 490static struct i2c_client *dm6446evm_msp; 491 492static int dm6446evm_msp_probe(struct i2c_client *client, 493 const struct i2c_device_id *id) 494{ 495 dm6446evm_msp = client; 496 return 0; 497} 498 499static int dm6446evm_msp_remove(struct i2c_client *client) 500{ 501 dm6446evm_msp = NULL; 502 return 0; 503} 504 505static const struct i2c_device_id dm6446evm_msp_ids[] = { 506 { "dm6446evm_msp", 0, }, 507 { /* end of list */ }, 508}; 509 510static struct i2c_driver dm6446evm_msp_driver = { 511 .driver.name = "dm6446evm_msp", 512 .id_table = dm6446evm_msp_ids, 513 .probe = dm6446evm_msp_probe, 514 .remove = dm6446evm_msp_remove, 515}; 516 517static int dm6444evm_msp430_get_pins(void) 518{ 519 static const char txbuf[2] = { 2, 4, }; 520 char buf[4]; 521 struct i2c_msg msg[2] = { 522 { 523 .flags = 0, 524 .len = 2, 525 .buf = (void __force *)txbuf, 526 }, 527 { 528 .flags = I2C_M_RD, 529 .len = 4, 530 .buf = buf, 531 }, 532 }; 533 int status; 534 535 if (!dm6446evm_msp) 536 return -ENXIO; 537 538 msg[0].addr = dm6446evm_msp->addr; 539 msg[1].addr = dm6446evm_msp->addr; 540 541 /* Command 4 == get input state, returns port 2 and port3 data 542 * S Addr W [A] len=2 [A] cmd=4 [A] 543 * RS Addr R [A] [len=4] A [cmd=4] A [port2] A [port3] N P 544 */ 545 status = i2c_transfer(dm6446evm_msp->adapter, msg, 2); 546 if (status < 0) 547 return status; 548 549 dev_dbg(&dm6446evm_msp->dev, 550 "PINS: %02x %02x %02x %02x\n", 551 buf[0], buf[1], buf[2], buf[3]); 552 553 return (buf[3] << 8) | buf[2]; 554} 555 556static int dm6444evm_mmc_get_cd(int module) 557{ 558 int status = dm6444evm_msp430_get_pins(); 559 560 return (status < 0) ? status : !(status & BIT(1)); 561} 562 563static int dm6444evm_mmc_get_ro(int module) 564{ 565 int status = dm6444evm_msp430_get_pins(); 566 567 return (status < 0) ? status : status & BIT(6 + 8); 568} 569 570static struct davinci_mmc_config dm6446evm_mmc_config = { 571 .get_cd = dm6444evm_mmc_get_cd, 572 .get_ro = dm6444evm_mmc_get_ro, 573 .wires = 4, 574}; 575 576static struct i2c_board_info __initdata i2c_info[] = { 577 { 578 I2C_BOARD_INFO("dm6446evm_msp", 0x23), 579 }, 580 { 581 I2C_BOARD_INFO("pcf8574", 0x38), 582 .platform_data = &pcf_data_u2, 583 }, 584 { 585 I2C_BOARD_INFO("pcf8574", 0x39), 586 .platform_data = &pcf_data_u18, 587 }, 588 { 589 I2C_BOARD_INFO("pcf8574", 0x3a), 590 .platform_data = &pcf_data_u35, 591 }, 592 { 593 I2C_BOARD_INFO("24c256", 0x50), 594 .platform_data = &eeprom_info, 595 }, 596 { 597 I2C_BOARD_INFO("tlv320aic33", 0x1b), 598 }, 599}; 600 601/* The msp430 uses a slow bitbanged I2C implementation (ergo 20 KHz), 602 * which requires 100 usec of idle bus after i2c writes sent to it. 603 */ 604static struct davinci_i2c_platform_data i2c_pdata = { 605 .bus_freq = 20 /* kHz */, 606 .bus_delay = 100 /* usec */, 607 .sda_pin = 44, 608 .scl_pin = 43, 609}; 610 611static void __init evm_init_i2c(void) 612{ 613 davinci_init_i2c(&i2c_pdata); 614 i2c_add_driver(&dm6446evm_msp_driver); 615 i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info)); 616} 617 618#define VENC_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) 619 620/* venc standard timings */ 621static struct vpbe_enc_mode_info dm644xevm_enc_std_timing[] = { 622 { 623 .name = "ntsc", 624 .timings_type = VPBE_ENC_STD, 625 .std_id = V4L2_STD_NTSC, 626 .interlaced = 1, 627 .xres = 720, 628 .yres = 480, 629 .aspect = {11, 10}, 630 .fps = {30000, 1001}, 631 .left_margin = 0x79, 632 .upper_margin = 0x10, 633 }, 634 { 635 .name = "pal", 636 .timings_type = VPBE_ENC_STD, 637 .std_id = V4L2_STD_PAL, 638 .interlaced = 1, 639 .xres = 720, 640 .yres = 576, 641 .aspect = {54, 59}, 642 .fps = {25, 1}, 643 .left_margin = 0x7e, 644 .upper_margin = 0x16, 645 }, 646}; 647 648/* venc dv preset timings */ 649static struct vpbe_enc_mode_info dm644xevm_enc_preset_timing[] = { 650 { 651 .name = "480p59_94", 652 .timings_type = VPBE_ENC_DV_TIMINGS, 653 .dv_timings = V4L2_DV_BT_CEA_720X480P59_94, 654 .interlaced = 0, 655 .xres = 720, 656 .yres = 480, 657 .aspect = {1, 1}, 658 .fps = {5994, 100}, 659 .left_margin = 0x80, 660 .upper_margin = 0x20, 661 }, 662 { 663 .name = "576p50", 664 .timings_type = VPBE_ENC_DV_TIMINGS, 665 .dv_timings = V4L2_DV_BT_CEA_720X576P50, 666 .interlaced = 0, 667 .xres = 720, 668 .yres = 576, 669 .aspect = {1, 1}, 670 .fps = {50, 1}, 671 .left_margin = 0x7e, 672 .upper_margin = 0x30, 673 }, 674}; 675 676/* 677 * The outputs available from VPBE + encoders. Keep the order same 678 * as that of encoders. First those from venc followed by that from 679 * encoders. Index in the output refers to index on a particular encoder. 680 * Driver uses this index to pass it to encoder when it supports more 681 * than one output. Userspace applications use index of the array to 682 * set an output. 683 */ 684static struct vpbe_output dm644xevm_vpbe_outputs[] = { 685 { 686 .output = { 687 .index = 0, 688 .name = "Composite", 689 .type = V4L2_OUTPUT_TYPE_ANALOG, 690 .std = VENC_STD_ALL, 691 .capabilities = V4L2_OUT_CAP_STD, 692 }, 693 .subdev_name = DM644X_VPBE_VENC_SUBDEV_NAME, 694 .default_mode = "ntsc", 695 .num_modes = ARRAY_SIZE(dm644xevm_enc_std_timing), 696 .modes = dm644xevm_enc_std_timing, 697 }, 698 { 699 .output = { 700 .index = 1, 701 .name = "Component", 702 .type = V4L2_OUTPUT_TYPE_ANALOG, 703 .capabilities = V4L2_OUT_CAP_DV_TIMINGS, 704 }, 705 .subdev_name = DM644X_VPBE_VENC_SUBDEV_NAME, 706 .default_mode = "480p59_94", 707 .num_modes = ARRAY_SIZE(dm644xevm_enc_preset_timing), 708 .modes = dm644xevm_enc_preset_timing, 709 }, 710}; 711 712static struct vpbe_config dm644xevm_display_cfg = { 713 .module_name = "dm644x-vpbe-display", 714 .i2c_adapter_id = 1, 715 .osd = { 716 .module_name = DM644X_VPBE_OSD_SUBDEV_NAME, 717 }, 718 .venc = { 719 .module_name = DM644X_VPBE_VENC_SUBDEV_NAME, 720 }, 721 .num_outputs = ARRAY_SIZE(dm644xevm_vpbe_outputs), 722 .outputs = dm644xevm_vpbe_outputs, 723}; 724 725static struct platform_device *davinci_evm_devices[] __initdata = { 726 &davinci_fb_device, 727 &rtc_dev, 728}; 729 730static void __init 731davinci_evm_map_io(void) 732{ 733 dm644x_init(); 734} 735 736static int davinci_phy_fixup(struct phy_device *phydev) 737{ 738 unsigned int control; 739 /* CRITICAL: Fix for increasing PHY signal drive strength for 740 * TX lockup issue. On DaVinci EVM, the Intel LXT971 PHY 741 * signal strength was low causing TX to fail randomly. The 742 * fix is to Set bit 11 (Increased MII drive strength) of PHY 743 * register 26 (Digital Config register) on this phy. */ 744 control = phy_read(phydev, 26); 745 phy_write(phydev, 26, (control | 0x800)); 746 return 0; 747} 748 749#define HAS_ATA IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710) 750 751#define HAS_NOR IS_ENABLED(CONFIG_MTD_PHYSMAP) 752 753#define HAS_NAND IS_ENABLED(CONFIG_MTD_NAND_DAVINCI) 754 755static __init void davinci_evm_init(void) 756{ 757 int ret; 758 struct clk *aemif_clk; 759 struct davinci_soc_info *soc_info = &davinci_soc_info; 760 761 ret = dm644x_gpio_register(); 762 if (ret) 763 pr_warn("%s: GPIO init failed: %d\n", __func__, ret); 764 765 aemif_clk = clk_get(NULL, "aemif"); 766 clk_prepare_enable(aemif_clk); 767 768 if (HAS_ATA) { 769 if (HAS_NAND || HAS_NOR) 770 pr_warning("WARNING: both IDE and Flash are " 771 "enabled, but they share AEMIF pins.\n" 772 "\tDisable IDE for NAND/NOR support.\n"); 773 davinci_init_ide(); 774 } else if (HAS_NAND || HAS_NOR) { 775 davinci_cfg_reg(DM644X_HPIEN_DISABLE); 776 davinci_cfg_reg(DM644X_ATAEN_DISABLE); 777 778 /* only one device will be jumpered and detected */ 779 if (HAS_NAND) { 780 platform_device_register(&davinci_evm_nandflash_device); 781 782 if (davinci_aemif_setup(&davinci_evm_nandflash_device)) 783 pr_warn("%s: Cannot configure AEMIF.\n", 784 __func__); 785 786 evm_leds[7].default_trigger = "nand-disk"; 787 if (HAS_NOR) 788 pr_warning("WARNING: both NAND and NOR flash " 789 "are enabled; disable one of them.\n"); 790 } else if (HAS_NOR) 791 platform_device_register(&davinci_evm_norflash_device); 792 } 793 794 platform_add_devices(davinci_evm_devices, 795 ARRAY_SIZE(davinci_evm_devices)); 796 evm_init_i2c(); 797 798 davinci_setup_mmc(0, &dm6446evm_mmc_config); 799 dm644x_init_video(&dm644xevm_capture_cfg, &dm644xevm_display_cfg); 800 801 davinci_serial_init(dm644x_serial_device); 802 dm644x_init_asp(&dm644x_evm_snd_data); 803 804 /* irlml6401 switches over 1A, in under 8 msec */ 805 davinci_setup_usb(1000, 8); 806 807 if (IS_BUILTIN(CONFIG_PHYLIB)) { 808 soc_info->emac_pdata->phy_id = DM644X_EVM_PHY_ID; 809 /* Register the fixup for PHY on DaVinci */ 810 phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK, 811 davinci_phy_fixup); 812 } 813} 814 815MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM") 816 /* Maintainer: MontaVista Software <source@mvista.com> */ 817 .atag_offset = 0x100, 818 .map_io = davinci_evm_map_io, 819 .init_irq = davinci_irq_init, 820 .init_time = davinci_timer_init, 821 .init_machine = davinci_evm_init, 822 .init_late = davinci_init_late, 823 .dma_zone_size = SZ_128M, 824 .restart = davinci_restart, 825MACHINE_END 826