Searched defs:ctrl_reg (Results 1 - 4 of 4) sorted by relevance
/arch/powerpc/platforms/52xx/ |
H A D | mpc52xx_pic.c | 178 u32 ctrl_reg, type; local 194 ctrl_reg = in_be32(&intr->ctrl); 195 ctrl_reg &= ~(0x3 << (22 - (l2irq * 2))); 196 ctrl_reg |= (type << (22 - (l2irq * 2))); 197 out_be32(&intr->ctrl, ctrl_reg);
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/arch/arc/mm/ |
H A D | cache_arc700.c | 305 unsigned int ctrl_reg; local 308 ctrl_reg = __before_dc_op(cacheop); 317 __after_dc_op(cacheop, ctrl_reg); 330 unsigned int ctrl_reg; local 334 ctrl_reg = __before_dc_op(cacheop); 338 __after_dc_op(cacheop, ctrl_reg);
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/arch/arm/kernel/ |
H A D | hw_breakpoint.c | 306 u32 ctrl_reg; local 315 ctrl_reg = encode_ctrl_reg(ctrl); 318 write_wb_reg(ARM_BASE_WCR, ctrl_reg); 319 if ((read_wb_reg(ARM_BASE_WCR) & ctrl_reg) == ctrl_reg) 696 u32 val, ctrl_reg, alignment_mask; local 733 ctrl_reg = read_wb_reg(ARM_BASE_WCR + i); 734 decode_ctrl_reg(ctrl_reg, &ctrl); 801 u32 ctrl_reg, val, addr; local 828 ctrl_reg [all...] |
/arch/arm64/kernel/ |
H A D | hw_breakpoint.c | 233 int i, max_slots, ctrl_reg, val_reg, reg_enable; local 239 ctrl_reg = AARCH64_DBG_REG_BCR; 246 ctrl_reg = AARCH64_DBG_REG_WCR; 272 write_wb_reg(ctrl_reg, i, 277 write_wb_reg(ctrl_reg, i, 0); 584 u32 ctrl_reg; local 608 ctrl_reg = read_wb_reg(AARCH64_DBG_REG_BCR, i); 609 decode_ctrl_reg(ctrl_reg, &ctrl); 660 u32 ctrl_reg; local 695 ctrl_reg [all...] |
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