Searched defs:dcfg (Results 1 - 8 of 8) sorted by relevance

/drivers/video/fbdev/geode/
H A Dvideo_cs5530.c102 u32 dcfg; local
104 dcfg = readl(par->vid_regs + CS5530_DISPLAY_CONFIG);
107 dcfg &= ~(CS5530_DCFG_CRT_SYNC_SKW_MASK | CS5530_DCFG_PWR_SEQ_DLY_MASK
114 dcfg |= (CS5530_DCFG_CRT_SYNC_SKW_INIT | CS5530_DCFG_PWR_SEQ_DLY_INIT
119 dcfg |= CS5530_DCFG_DAC_PWR_EN;
120 dcfg |= CS5530_DCFG_HSYNC_EN | CS5530_DCFG_VSYNC_EN;
124 dcfg |= CS5530_DCFG_FP_PWR_EN;
125 dcfg |= CS5530_DCFG_FP_DATA_EN;
130 dcfg |= CS5530_DCFG_CRT_HSYNC_POL;
132 dcfg |
140 u32 dcfg; local
[all...]
H A Ddisplay_gx.c64 u32 gcfg, dcfg; local
72 dcfg = read_dc(par, DC_DISPLAY_CFG);
75 dcfg &= ~DC_DISPLAY_CFG_TGEN;
76 write_dc(par, DC_DISPLAY_CFG, dcfg);
95 dcfg = 0;
112 dcfg |= DC_DISPLAY_CFG_GDEN | DC_DISPLAY_CFG_VDEN |
118 dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP;
121 dcfg |= DC_DISPLAY_CFG_DISP_MODE_16BPP;
124 dcfg |= DC_DISPLAY_CFG_DISP_MODE_24BPP;
125 dcfg |
[all...]
H A Dvideo_gx.c239 u32 dcfg, misc; local
242 dcfg = read_vp(par, VP_DCFG);
245 dcfg &= ~(VP_DCFG_VSYNC_EN | VP_DCFG_HSYNC_EN);
246 write_vp(par, VP_DCFG, dcfg);
249 dcfg &= ~(VP_DCFG_CRT_SYNC_SKW
254 dcfg |= VP_DCFG_CRT_SYNC_SKW_DEFAULT;
257 dcfg |= VP_DCFG_HSYNC_EN | VP_DCFG_VSYNC_EN;
274 dcfg |= VP_DCFG_CRT_HSYNC_POL;
276 dcfg |= VP_DCFG_CRT_VSYNC_POL;
286 dcfg |
301 u32 dcfg, fp_pm; local
[all...]
H A Dlxfb_ops.c352 unsigned int gcfg, dcfg; local
441 dcfg = DC_DISPLAY_CFG_VDEN; /* Enable video data */
442 dcfg |= DC_DISPLAY_CFG_GDEN; /* Enable graphics */
443 dcfg |= DC_DISPLAY_CFG_TGEN; /* Turn on the timing generator */
444 dcfg |= DC_DISPLAY_CFG_TRUP; /* Update timings immediately */
445 dcfg |= DC_DISPLAY_CFG_PALB; /* Palette bypass in > 8 bpp modes */
446 dcfg |= DC_DISPLAY_CFG_VISL;
447 dcfg |= DC_DISPLAY_CFG_DCEN; /* Always center the display */
453 dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP;
457 dcfg |
528 u32 dcfg, misc, fp_pm; local
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/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_dcb_nl.c51 struct ixgbe_dcb_config *dcfg = &adapter->dcb_cfg; local
71 dst = &dcfg->tc_config[i - DCB_PG_ATTR_TC_0];
120 if (dcfg->bw_percentage[tx][j] != scfg->bw_percentage[tx][j]) {
121 dcfg->bw_percentage[tx][j] = scfg->bw_percentage[tx][j];
124 if (dcfg->bw_percentage[rx][j] != scfg->bw_percentage[rx][j]) {
125 dcfg->bw_percentage[rx][j] = scfg->bw_percentage[rx][j];
132 if (dcfg->tc_config[j].dcb_pfc != scfg->tc_config[j].dcb_pfc) {
133 dcfg->tc_config[j].dcb_pfc = scfg->tc_config[j].dcb_pfc;
138 if (dcfg->pfc_mode_enable != scfg->pfc_mode_enable) {
139 dcfg
[all...]
/drivers/net/ethernet/cadence/
H A Dmacb.c2031 u32 dcfg; local
2053 dcfg = gem_readl(bp, DCFG1);
2054 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
2056 dcfg = gem_readl(bp, DCFG2);
2057 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
/drivers/usb/dwc2/
H A Dgadget.c1084 u32 dcfg; local
1111 dcfg = readl(hsotg->regs + DCFG);
1112 dcfg &= ~DCFG_DEVADDR_MASK;
1113 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1115 writel(dcfg, hsotg->regs + DCFG);
/drivers/usb/dwc3/
H A Dcore.h641 * @dcfg: saved contents of DCFG register
710 u32 dcfg; member in struct:dwc3

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