Searched defs:div2 (Results 1 - 11 of 11) sorted by relevance

/drivers/media/tuners/
H A Dmt2060.c164 u32 div1,num1,div2,num2; local
201 div2 = num2 / 8192;
220 b[5] = ((num2 >>12) & 1) | (div2 << 1);
224 dprintk("PLL div1=%d num1=%d div2=%d num2=%d",(int)div1,(int)num1,(int)div2,(int)num2);
H A Dmt2131.c103 u32 div1, num1, div2, num2; local
125 div2 = num2 / 8192;
154 b[6] = div2;
159 dprintk(1, "PLL div1=%d num1=%d div2=%d num2=%d\n",
160 (int)div1, (int)num1, (int)div2, (int)num2);
/drivers/staging/comedi/drivers/
H A D8253.h40 unsigned int div1, div2; local
51 div2 = *d2 ? *d2 : max_count;
52 divider = div1 * div2;
53 if (div1 * div2 * i8253_osc_base == *nanosec &&
54 div1 > 1 && div1 <= max_count && div2 > 1 && div2 <= max_count &&
56 divider > div1 && divider > div2 &&
70 div2 = max_count;
71 start = divider / div2;
76 for (div2
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H A Dadl_pci9111.c143 unsigned int div2; member in struct:pci9111_private_data
183 i8254_write(timer_base, 1, 2, dev_private->div2);
352 &dev_private->div2,
693 dev_private->div2 = 0;
H A Dadl_pci9118.c517 unsigned int *div1, unsigned int *div2,
523 *div2 = *tim1 / I8254_OSC_BASE_4MHZ; /* scan timer */
524 *div2 = *div2 / *div1; /* major timer is c1*c2 */
525 if (*div2 < chans)
526 *div2 = chans;
532 if (*div2 < (chans + 2))
533 *div2 = chans + 2;
536 *tim1 = *div1 * *div2 * I8254_OSC_BASE_4MHZ;
513 pci9118_calc_divisors(struct comedi_device *dev, struct comedi_subdevice *s, unsigned int *tim1, unsigned int *tim2, unsigned int flags, int chans, unsigned int *div1, unsigned int *div2, unsigned int chnsshfront) argument
/drivers/cpufreq/
H A Dpxa2xx-cpufreq.c63 unsigned int div2; member in struct:__anon483
287 new_freq_cpu / 1000, (pxa_freq_settings[idx].div2) ?
312 if (pxa_freq_settings[idx].div2) {
/drivers/spi/
H A Dspi-omap-uwire.c323 int div2; local
379 div2 = (rate / div1 + hz - 1) / hz;
380 if (div2 <= 8)
398 switch (div2) {
/drivers/clk/
H A Dclk-vt8500.c387 u32 mul, div1, div2; local
395 for (div2 = 3; div2 >= 0; div2--)
397 tclk = parent_rate * mul / (div1 * (1 << div2));
405 *divisor2 = div2;
413 best_div2 = div2;
455 u32 mul, div1, div2; local
463 for (div2 = 7; div2 >
499 u32 mul, div1, div2; local
543 u32 filter, mul, div1, div2; local
586 u32 filter, mul, div1, div2; local
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/drivers/media/dvb-frontends/
H A Dstb0899_algo.c1286 int div1, div2, rem1, rem2; local
1289 div2 = config->btr_nco_bits - div1 - 1;
1298 intval2 = bTrNomFreq / (1 << div2);
1301 rem2 = bTrNomFreq % (1 << div2);
1303 srate = (intval1 * intval2) + ((intval1 * rem2) / (1 << div2)) + ((intval2 * rem1) / (1 << div1));
/drivers/video/fbdev/
H A Dcyber2000fb.c654 * fclock = fpll / div2
660 * div2 = 2^(reg0xb1.7:6)
670 u_int div2, t_div1, best_div1, best_mult; local
676 * find div2 such that 115MHz < fpll < 260MHz
677 * and 0 <= div2 < 4
679 for (div2 = 0; div2 < 4; div2++) {
682 new_pll = pll_ps / cfb->divisors[div2];
689 if (div2
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H A Damifb.c545 #define div2(v) ((v)>>1) macro
1022 #define vsstrt2hw(vsstrt) (div2(vsstrt))
1023 #define vsstop2hw(vsstop) (div2(vsstop))
1024 #define vtotal2hw(vtotal) (div2(vtotal) - 1)
1031 #define vbstrt2hw(vbstrt) (div2(vbstrt))
1032 #define vbstop2hw(vbstop) (div2(vbstop))

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