Searched defs:enable_mask (Results 1 - 24 of 24) sorted by relevance

/drivers/clk/qcom/
H A Dclk-regmap.h26 * @enable_mask: mask when using regmap enable/disable ops
27 * @enable_is_inverted: flag to indicate set enable_mask bits to disable
34 unsigned int enable_mask; member in struct:clk_regmap
H A Dclk-pll.c163 u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N; local
170 enabled = (mode & enable_mask) == enable_mask;
/drivers/clk/mmp/
H A Dclk-apmu.c26 u32 enable_mask; member in struct:clk_apmu
39 data = readl_relaxed(apmu->base) | apmu->enable_mask;
57 data = readl_relaxed(apmu->base) & ~apmu->enable_mask;
70 void __iomem *base, u32 enable_mask, spinlock_t *lock)
87 apmu->enable_mask = enable_mask;
69 mmp_clk_register_apmu(const char *name, const char *parent_name, void __iomem *base, u32 enable_mask, spinlock_t *lock) argument
/drivers/acpi/acpica/
H A Dhwgpe.c96 u32 enable_mask; local
110 status = acpi_hw_read(&enable_mask, &gpe_register_info->enable_address);
131 ACPI_SET_BIT(enable_mask, register_bit);
136 ACPI_CLEAR_BIT(enable_mask, register_bit);
147 status = acpi_hw_write(enable_mask, &gpe_register_info->enable_address);
/drivers/gpu/drm/radeon/
H A Dkv_smc.c54 int kv_dpm_get_enable_mask(struct radeon_device *rdev, u32 *enable_mask) argument
61 *enable_mask = RREG32_SMC(SMC_SYSCON_MSG_ARG_0);
H A Ddce6_afmt.c287 u8 enable_mask)
293 enable_mask ? AUDIO_ENABLED : 0);
285 dce6_audio_enable(struct radeon_device *rdev, struct r600_audio_pin *pin, u8 enable_mask) argument
H A Devergreen_hdmi.c44 u8 enable_mask)
51 if (enable_mask) {
53 if (enable_mask & 1)
55 if (enable_mask & 2)
57 if (enable_mask & 4)
59 if (enable_mask & 8)
42 dce4_audio_enable(struct radeon_device *rdev, struct r600_audio_pin *pin, u8 enable_mask) argument
H A Dr600_hdmi.c166 u8 enable_mask)
173 if (enable_mask) {
175 if (enable_mask & 1)
177 if (enable_mask & 2)
179 if (enable_mask & 4)
181 if (enable_mask & 8)
164 r600_audio_enable(struct radeon_device *rdev, struct r600_audio_pin *pin, u8 enable_mask) argument
H A Dkv_dpm.h66 u32 enable_mask; member in struct:kv_lcac_config_reg
189 int kv_dpm_get_enable_mask(struct radeon_device *rdev, u32 *enable_mask);
H A Dkv_dpm.c274 local_cac_reg->enable_mask);
2027 u32 enable_mask, i; local
2029 ret = kv_dpm_get_enable_mask(rdev, &enable_mask);
2034 if (enable_mask & (1 << i))
2047 u32 enable_mask, i; local
2049 ret = kv_dpm_get_enable_mask(rdev, &enable_mask);
2054 if (enable_mask & (1 << i))
/drivers/regulator/
H A Daat2870-regulator.c38 u8 enable_mask; member in struct:aat2870_regulator
74 return aat2870->update(aat2870, ri->enable_addr, ri->enable_mask,
75 ri->enable_mask);
83 return aat2870->update(aat2870, ri->enable_addr, ri->enable_mask, 0);
97 return val & ri->enable_mask ? 1 : 0;
153 ri->enable_mask = 0x1 << ri->enable_shift;
H A Dpbias-regulator.c32 u32 enable_mask; member in struct:pbias_reg_info
63 .enable_mask = BIT(1),
71 .enable_mask = BIT(9),
79 .enable_mask = BIT(26) | BIT(25) | BIT(22),
87 .enable_mask = BIT(27) | BIT(25) | BIT(26),
160 drvdata[data_idx].desc.enable_mask = info->enable_mask;
H A Das3722-regulator.c68 u8 enable_mask; member in struct:as3722_register_mapping
97 .enable_mask = AS3722_SDn_CTRL(0),
109 .enable_mask = AS3722_SDn_CTRL(1),
122 .enable_mask = AS3722_SDn_CTRL(2),
136 .enable_mask = AS3722_SDn_CTRL(3),
150 .enable_mask = AS3722_SDn_CTRL(4),
164 .enable_mask = AS3722_SDn_CTRL(5),
177 .enable_mask = AS3722_SDn_CTRL(6),
190 .enable_mask = AS3722_LDO0_CTRL,
202 .enable_mask
[all...]
/drivers/clk/
H A Dclk-palmas.c37 unsigned int enable_mask; member in struct:palmas_clk32k_desc
70 cinfo->clk_desc->enable_mask,
71 cinfo->clk_desc->enable_mask);
95 cinfo->clk_desc->enable_mask, 0);
117 return !!(val & cinfo->clk_desc->enable_mask);
141 .enable_mask = PALMAS_CLK32KG_CTRL_MODE_ACTIVE,
157 .enable_mask = PALMAS_CLK32KG_CTRL_MODE_ACTIVE,
/drivers/clk/mvebu/
H A Dclk-corediv.c81 u32 enable_mask = BIT(desc->fieldbit) << soc_desc->enable_bit_offset; local
83 return !!(readl(corediv->reg) & enable_mask);
/drivers/clocksource/
H A Dtime-armada-370-xp.c79 static u32 enable_mask; variable
119 local_timer_ctrl_clrset(TIMER0_RELOAD_EN, enable_mask);
138 local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN | enable_mask);
237 enable_mask = TIMER0_EN;
240 enable_mask = TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT);
261 TIMER0_RELOAD_EN | enable_mask,
262 TIMER0_RELOAD_EN | enable_mask);
/drivers/gpu/drm/via/
H A Dvia_drv.h58 uint32_t enable_mask; member in struct:drm_via_irq
/drivers/gpu/drm/exynos/
H A Dexynos_dp_core.h157 unsigned int enable_mask; member in struct:exynos_dp_device
/drivers/tty/
H A Dsysrq.c100 .enable_mask = SYSRQ_ENABLE_LOG,
113 .enable_mask = SYSRQ_ENABLE_KEYBOARD,
129 .enable_mask = SYSRQ_ENABLE_KEYBOARD,
147 .enable_mask = SYSRQ_ENABLE_DUMP,
160 .enable_mask = SYSRQ_ENABLE_BOOT,
171 .enable_mask = SYSRQ_ENABLE_SYNC,
193 .enable_mask = SYSRQ_ENABLE_REMOUNT,
257 .enable_mask = SYSRQ_ENABLE_DUMP,
272 .enable_mask = SYSRQ_ENABLE_DUMP,
283 .enable_mask
1028 sysrq_toggle_support(int enable_mask) argument
[all...]
/drivers/iio/imu/
H A Dadis16480.c436 unsigned int enable_mask, offset, reg; local
442 enable_mask = BIT(offset + 2);
448 if (!(val & enable_mask))
460 unsigned int enable_mask, offset, reg; local
468 enable_mask = BIT(offset + 2);
475 val &= ~enable_mask;
491 val |= enable_mask;
/drivers/gpu/drm/i915/
H A Di915_irq.c586 u32 enable_mask, u32 status_mask)
593 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
595 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
596 pipe_name(pipe), enable_mask, status_mask))
599 if ((pipestat & enable_mask) == enable_mask)
605 pipestat |= enable_mask | status_mask;
612 u32 enable_mask, u32 status_mask)
619 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
621 "pipe %c: enable_mask
585 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, u32 enable_mask, u32 status_mask) argument
611 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, u32 enable_mask, u32 status_mask) argument
637 u32 enable_mask = status_mask << 16; local
667 u32 enable_mask; local
681 u32 enable_mask; local
3826 u32 enable_mask = I915_DISPLAY_PORT_INTERRUPT | local
4151 u32 enable_mask; local
4373 u32 enable_mask; local
[all...]
/drivers/net/ethernet/via/
H A Dvia-rhine.c828 u16 enable_mask = RHINE_EVENT & 0xffff; local
859 enable_mask &= ~RHINE_EVENT_SLOW;
865 iowrite16(enable_mask, ioaddr + IntrEnable);
/drivers/isdn/hardware/eicon/
H A Dmessage.c9590 static void dtmf_enable_receiver(PLCI *plci, byte enable_mask) argument
9596 (char *)(FILE_), __LINE__, enable_mask));
9598 if (enable_mask != 0)
/drivers/net/ethernet/realtek/
H A Dr8169.c7453 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow; local
7467 enable_mask &= ~tp->event_slow;
7475 rtl_irq_enable(tp, enable_mask);

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