Searched defs:engine_clock (Results 1 - 8 of 8) sorted by relevance

/drivers/gpu/drm/radeon/
H A Drv730_dpm.c41 u32 engine_clock,
58 engine_clock, false, &dividers);
70 tmp = (u64) engine_clock * reference_divider * post_divider * 16384;
93 u32 vco_freq = engine_clock * post_divider;
109 sclk->sclk_value = cpu_to_be32(engine_clock);
120 u32 engine_clock, u32 memory_clock,
40 rv730_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, RV770_SMC_SCLK_VALUE *sclk) argument
119 rv730_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, LPRV7XX_SMC_MCLK_VALUE mclk) argument
H A Drv740_dpm.c121 int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, argument
138 engine_clock, false, &dividers);
144 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
161 u32 vco_freq = engine_clock * dividers.post_div;
177 sclk->sclk_value = cpu_to_be32(engine_clock);
188 u32 engine_clock, u32 memory_clock,
187 rv740_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, RV7XX_SMC_MCLK_VALUE *mclk) argument
H A Dcypress_dpm.c474 u32 engine_clock, u32 memory_clock,
904 u32 engine_clock, u32 memory_clock)
908 u32 result = (4 * multiplier * engine_clock) / (memory_clock / 2);
473 cypress_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, RV7XX_SMC_MCLK_VALUE *mclk, bool strobe_mode, bool dll_state_on) argument
903 cypress_calculate_burst_time(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock) argument
H A Drv6xx_dpm.c783 u32 engine_clock)
792 return ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
782 calculate_memory_refresh_rate(struct radeon_device *rdev, u32 engine_clock) argument
H A Dni_dpm.c1999 u32 engine_clock,
2018 engine_clock, false, &dividers);
2025 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834;
2042 u32 vco_freq = engine_clock * dividers.post_div;
2058 sclk->sclk_value = engine_clock;
2070 u32 engine_clock,
2076 ret = ni_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
2161 u32 engine_clock,
1998 ni_calculate_sclk_params(struct radeon_device *rdev, u32 engine_clock, NISLANDS_SMC_SCLK_VALUE *sclk) argument
2069 ni_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, NISLANDS_SMC_SCLK_VALUE *sclk) argument
2160 ni_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, NISLANDS_SMC_MCLK_VALUE *mclk, bool strobe_mode, bool dll_state_on) argument
H A Drv770_dpm.c385 u32 engine_clock, u32 memory_clock,
483 u32 engine_clock,
505 engine_clock, false, &dividers);
516 tmp = (u64) engine_clock * reference_divider * post_divider * 16384;
538 u32 vco_freq = engine_clock * post_divider;
554 sclk->sclk_value = cpu_to_be32(engine_clock);
721 u32 engine_clock)
732 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
384 rv770_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, RV7XX_SMC_MCLK_VALUE *mclk) argument
482 rv770_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, RV770_SMC_SCLK_VALUE *sclk) argument
720 rv770_calculate_memory_refresh_rate(struct radeon_device *rdev, u32 engine_clock) argument
H A Dci_dpm.c2682 u32 engine_clock,
2698 engine_clock, false, &dividers);
2711 u32 vco_freq = engine_clock * dividers.post_div;
2727 sclk->SclkFrequency = engine_clock;
2738 u32 engine_clock,
2745 ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level);
2751 engine_clock, &graphic_level->MinVddc);
2755 graphic_level->SclkFrequency = engine_clock;
2763 engine_clock,
2779 engine_clock,
2681 ci_calculate_sclk_params(struct radeon_device *rdev, u32 engine_clock, SMU7_Discrete_GraphicsLevel *sclk) argument
2737 ci_populate_single_graphic_level(struct radeon_device *rdev, u32 engine_clock, u16 sclk_activity_level_t, SMU7_Discrete_GraphicsLevel *graphic_level) argument
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H A Dsi_dpm.c1756 u32 engine_clock,
4154 u32 engine_clock)
4167 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4662 u32 engine_clock,
4681 engine_clock, false, &dividers);
4687 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4704 u32 vco_freq = engine_clock * dividers.post_div;
4720 sclk->sclk_value = engine_clock;
4732 u32 engine_clock,
4738 ret = si_calculate_sclk_params(rdev, engine_clock,
4153 si_calculate_memory_refresh_rate(struct radeon_device *rdev, u32 engine_clock) argument
4661 si_calculate_sclk_params(struct radeon_device *rdev, u32 engine_clock, SISLANDS_SMC_SCLK_VALUE *sclk) argument
4731 si_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, SISLANDS_SMC_SCLK_VALUE *sclk) argument
4752 si_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, SISLANDS_SMC_MCLK_VALUE *mclk, bool strobe_mode, bool dll_state_on) argument
[all...]

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