Searched defs:insn (Results 126 - 150 of 156) sorted by relevance

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/arch/mips/cavium-octeon/
H A Dsetup.c1009 u32 insn; local
1012 foo = &insn;
1023 : "=r" (insn) : : "$31", "memory");
1025 if ((insn >> 26) != 0x33)
1028 if (((insn >> 16) & 0x1f) != 28)
1030 "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).", insn);
/arch/mips/include/asm/
H A Duaccess.h261 #define __GET_DW(val, insn, ptr) __get_data_asm_ll32(val, insn, ptr)
264 #define __GET_DW(val, insn, ptr) __get_data_asm(val, insn, ptr)
310 #define __get_data_asm(val, insn, addr) \
315 "1: "insn("%1", "%3")" \n" \
317 " .insn \n" \
335 #define __get_data_asm_ll32(val, insn, addr) \
343 "1: " insn("%1", "(%3)")" \n" \
344 "2: " insn("
1466 unsigned long insn; member in struct:exception_table_entry
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/arch/mips/kernel/
H A Dvpe.c340 /* Sign extend the addend we extract from the lo insn. */
347 unsigned long insn; local
363 insn = *l->addr;
364 val = ((insn & 0xffff) << 16) + vallo;
373 insn = (insn & ~0xffff) | val;
374 *l->addr = insn;
H A Dtraps.c224 unsigned int insn; local
225 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
229 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
1577 reg_val & (1<<31) ? "data" : "insn");
1631 reg_val & (1<<31) ? "data" : "insn");
1829 u32 insn; local
1834 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1);
1836 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2);
1838 h[0] = (insn >> 1
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/arch/sh/kernel/
H A Ddisassemble.c292 static void print_sh_insn(u32 memaddr, u16 insn) argument
295 int nibs[4] = { (insn >> 12) & 0xf, (insn >> 8) & 0xf, (insn >> 4) & 0xf, insn & 0xf};
560 unsigned short insn; local
562 if (__get_user(insn, pc + i)) {
568 print_sh_insn((unsigned long)(pc + i), insn);
H A Ddwarf.c406 unsigned char insn; local
414 insn = __raw_readb(current_insn++);
420 switch (DW_CFA_opcode(insn)) {
422 delta = DW_CFA_operand(insn);
428 reg = DW_CFA_operand(insn);
438 reg = DW_CFA_operand(insn);
447 switch (insn) {
546 pr_debug("unhandled DWARF instruction 0x%x\n", insn);
/arch/sh/math-emu/
H A Dmath.c507 unsigned short insn = *(unsigned short *)regs->pc; local
512 (insn >> 12) & 0xf,
513 (insn >> 8) & 0xf,
514 (insn >> 4) & 0xf,
515 insn & 0xf};
522 nextpc = regs->pc + 4 + ((short) ((insn & 0xfff) << 4) >> 3);
526 nextpc = regs->pc + 4 + ((char) (insn & 0xff) << 1);
534 nextpc = regs->pc + 4 + ((char) (insn & 0xff) << 1);
544 } else if (insn == 0x000b) { /* rts */
549 finsn = insn;
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/arch/sparc/kernel/
H A Dptrace_64.c859 unsigned int insn; member in struct:compat_fps::compat_fq
H A Dvisemul.c293 static void edge(struct pt_regs *regs, unsigned int insn, unsigned int opf) argument
298 maybe_flush_windows(RS1(insn), RS2(insn), RD(insn), 0);
299 orig_rs1 = rs1 = fetch_reg(RS1(insn), regs);
300 orig_rs2 = rs2 = fetch_reg(RS2(insn), regs);
349 store_reg(regs, rd_val, RD(insn));
371 static void array(struct pt_regs *regs, unsigned int insn, unsigned int opf) argument
376 maybe_flush_windows(RS1(insn), RS2(insn), R
405 bmask(struct pt_regs *regs, unsigned int insn) argument
421 bshuffle(struct pt_regs *regs, unsigned int insn) argument
447 pdist(struct pt_regs *regs, unsigned int insn) argument
476 pformat(struct pt_regs *regs, unsigned int insn, unsigned int opf) argument
588 pmul(struct pt_regs *regs, unsigned int insn, unsigned int opf) argument
704 pcmp(struct pt_regs *regs, unsigned int insn, unsigned int opf) argument
803 vis_emul(struct pt_regs *regs, unsigned int insn) argument
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H A Dtraps_64.c285 printk("EX_TABLE: insn<%016lx> fixup<%016lx>\n",
337 printk("EX_TABLE: insn<%016lx> fixup<%016lx>\n",
1920 unsigned int insn; local
1926 insn = *(unsigned int *) regs->tpc;
1928 addr = compute_effective_address(regs, insn, 0);
1930 printk("%s: insn effective address [0x%016llx]\n",
2444 u32 insn; local
2455 if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
2456 if ((insn & 0xc1ffc000) == 0x81700000) /* POPC */ {
2457 if (handle_popc(insn, reg
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/arch/sparc/math-emu/
H A Dmath_64.c170 u32 insn = 0; local
191 if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
192 if ((insn & 0xc1f80000) == 0x81a00000) /* FPOP1 */ {
193 switch ((insn >> 5) & 0x1ff) {
260 else if ((insn & 0xc1f80000) == 0x81a80000) /* FPOP2 */ {
262 switch ((insn >> 5) & 0x1ff) {
271 if (!((insn >> 11) & 3))
274 XR = current_thread_info()->xfsr[0] >> (30 + ((insn >> 10) & 0x6));
277 switch ((insn >> 14) & 0x7) {
287 if ((insn >> 1
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/arch/tile/kernel/
H A Dunaligned.c69 tilegx_bundle_bits insn[14]; member in struct:unaligned_jit_fragment
1032 frag.insn[n++] =
1038 frag.insn[n++] =
1044 frag.insn[n] = jit_x1_addi(ra, ra, 1);
1046 frag.insn[n] = jit_x1_addi(ra, ra,
1051 frag.insn[n] |= jit_x0_fnop();
1053 frag.insn[n] |= jit_x0_rotli(rb, rb, 32);
1055 frag.insn[n] |= jit_x0_rotli(rb, rb, 16);
1059 frag.insn[n++] = bundle_2;
1060 frag.insn[
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/arch/x86/kernel/kprobes/
H A Dcore.c58 #include <asm/insn.h>
121 } __packed *insn; local
123 insn = (struct __arch_relative_insn *)from;
124 insn->raddr = (s32)((long)(to) - ((long)(from) + 5));
125 insn->op = op;
145 static kprobe_opcode_t *skip_prefixes(kprobe_opcode_t *insn) argument
149 attr = inat_get_opcode_attribute((insn_byte_t)*insn);
151 insn++;
152 attr = inat_get_opcode_attribute((insn_byte_t)*insn);
156 insn
270 struct insn insn; local
306 is_IF_modifier(kprobe_opcode_t *insn) argument
331 struct insn insn; local
801 kprobe_opcode_t *insn = p->ainsn.insn; local
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/arch/x86/kernel/
H A Duprobes.c31 #include <asm/insn.h>
35 /* Adjust IP back to vicinity of actual insn */
38 /* Adjust the return address of a call insn */
53 #define OPCODE1(insn) ((insn)->opcode.bytes[0])
54 #define OPCODE2(insn) ((insn)->opcode.bytes[1])
55 #define OPCODE3(insn) ((insn)->opcode.bytes[2])
56 #define MODRM_REG(insn) X86_MODRM_RE
201 is_prefix_bad(struct insn *insn) argument
218 uprobe_init_insn(struct arch_uprobe *auprobe, struct insn *insn, bool x86_64) argument
277 riprel_analyze(struct arch_uprobe *auprobe, struct insn *insn) argument
440 riprel_analyze(struct arch_uprobe *auprobe, struct insn *insn) argument
619 branch_clear_offset(struct arch_uprobe *auprobe, struct insn *insn) argument
645 branch_setup_xol_ops(struct arch_uprobe *auprobe, struct insn *insn) argument
700 struct insn insn; local
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/arch/ia64/kernel/
H A Dmodule.c139 struct insn;
142 bundle (const struct insn *insn) argument
144 return (uint64_t) insn & ~0xfUL;
148 slot (const struct insn *insn) argument
150 return (uint64_t) insn & 0x3;
154 apply_imm64 (struct module *mod, struct insn *insn, uint64_t val) argument
156 if (slot(insn) !
166 apply_imm60(struct module *mod, struct insn *insn, uint64_t val) argument
183 apply_imm22(struct module *mod, struct insn *insn, uint64_t val) argument
198 apply_imm21b(struct module *mod, struct insn *insn, uint64_t val) argument
547 get_plt(struct module *mod, const struct insn *insn, uint64_t value, int *okp) argument
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H A Dunaligned.c1302 load_store_t insn; member in union:__anon1784
1385 "ld.x6=0x%x ld.m=%d ld.op=%d\n", opcode, u.insn.qp, u.insn.r1, u.insn.imm,
1386 u.insn.r3, u.insn.x, u.insn.hint, u.insn.x6_sz, u.insn.m, u.insn
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H A Dunwind_i.h163 struct unw_insn insn[UNW_MAX_SCRIPT_LEN]; member in struct:unw_script
H A Dunwind.c1348 script_emit (struct unw_script *script, struct unw_insn insn)
1355 script->insn[script->count++] = insn;
1363 struct unw_insn insn;
1397 insn.opc = opc;
1398 insn.dst = unw.preg_index[i];
1399 insn.val = val;
1400 script_emit(script, insn);
1409 struct unw_insn insn;
1482 insn
1345 script_emit(struct unw_script *script, struct unw_insn insn) argument
1360 struct unw_insn insn; local
1406 struct unw_insn insn; local
1535 struct unw_insn insn; local
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/arch/mips/kvm/
H A Demulate.c46 union mips_instruction insn; local
55 insn.word = kvm_get_inst((uint32_t *) epc, vcpu);
57 if (insn.word == KVM_INVALID_INST)
60 switch (insn.i_format.opcode) {
63 switch (insn.r_format.func) {
65 arch->gprs[insn.r_format.rd] = epc + 8;
68 nextpc = arch->gprs[insn.r_format.rs];
79 switch (insn.i_format.rt) {
82 if ((long)arch->gprs[insn.i_format.rs] < 0)
83 epc = epc + 4 + (insn
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/arch/powerpc/math-emu/
H A Dmath.c230 u32 insn = 0; local
236 if (get_user(insn, (u32 *)pc))
239 switch (insn >> 26) {
250 switch ((insn >> 1) & 0x3ff) {
266 switch ((insn >> 1) & 0x1f) {
284 if (insn & 0x20) {
285 switch ((insn >> 1) & 0x1f) {
304 switch ((insn >> 1) & 0x3ff) {
331 op0 = (void *)&current->thread.TS_FPR((insn >> 21) & 0x1f);
332 op1 = (void *)&current->thread.TS_FPR((insn >> 1
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/arch/x86/kernel/cpu/
H A Dperf_event_intel_ds.c6 #include <asm/insn.h>
754 * We sampled a branch insn, rewind using the LBR stack
776 struct insn insn; local
783 insn_init(&insn, kaddr, is_64bit);
784 insn_get_length(&insn);
786 to += insn.length;
787 kaddr += insn.length;
H A Dperf_event_intel_lbr.c6 #include <asm/insn.h>
466 struct insn insn; local
521 insn_init(&insn, addr, is64);
522 insn_get_opcode(&insn);
524 switch (insn.opcode.bytes[0]) {
526 switch (insn.opcode.bytes[1]) {
568 insn_get_modrm(&insn);
569 ext = (insn.modrm.bytes[0] >> 3) & 0x7;
/arch/arm/kernel/
H A Dkprobes-test.c829 coverage_add_registers(struct coverage_entry *entry, kprobe_opcode_t insn) argument
835 int reg = (insn >> i) & 0xf;
878 if (!is_writeback(insn))
896 static void coverage_add(kprobe_opcode_t insn) argument
914 if ((insn & h->mask.bits) != h->value.bits)
928 coverage_add_registers(entry, insn);
/arch/mips/mm/
H A Duasm.c62 struct insn { struct
138 build_insn(buf, insn##op, a, b, c); \
145 build_insn(buf, insn##op, b, c, a); \
152 build_insn(buf, insn##op, b, a, c); \
159 build_insn(buf, insn##op, c, b, a); \
166 build_insn(buf, insn##op, b, c, a); \
173 build_insn(buf, insn##op, a, b, c); \
180 build_insn(buf, insn##op, c, a, b); \
187 build_insn(buf, insn##op, b, a, c); \
194 build_insn(buf, insn##o
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/arch/sh/include/asm/
H A Ddwarf.h357 static inline unsigned int DW_CFA_opcode(unsigned long insn) argument
359 return (insn & 0xc0);
362 static inline unsigned int DW_CFA_operand(unsigned long insn) argument
364 return (insn & 0x3f);

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