1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2004-2007 Cavium Networks 7 * Copyright (C) 2008, 2009 Wind River Systems 8 * written by Ralf Baechle <ralf@linux-mips.org> 9 */ 10#include <linux/compiler.h> 11#include <linux/vmalloc.h> 12#include <linux/init.h> 13#include <linux/kernel.h> 14#include <linux/console.h> 15#include <linux/delay.h> 16#include <linux/export.h> 17#include <linux/interrupt.h> 18#include <linux/io.h> 19#include <linux/serial.h> 20#include <linux/smp.h> 21#include <linux/types.h> 22#include <linux/string.h> /* for memset */ 23#include <linux/tty.h> 24#include <linux/time.h> 25#include <linux/platform_device.h> 26#include <linux/serial_core.h> 27#include <linux/serial_8250.h> 28#include <linux/of_fdt.h> 29#include <linux/libfdt.h> 30#include <linux/kexec.h> 31 32#include <asm/processor.h> 33#include <asm/reboot.h> 34#include <asm/smp-ops.h> 35#include <asm/irq_cpu.h> 36#include <asm/mipsregs.h> 37#include <asm/bootinfo.h> 38#include <asm/sections.h> 39#include <asm/time.h> 40 41#include <asm/octeon/octeon.h> 42#include <asm/octeon/pci-octeon.h> 43#include <asm/octeon/cvmx-mio-defs.h> 44 45extern struct plat_smp_ops octeon_smp_ops; 46 47#ifdef CONFIG_PCI 48extern void pci_console_init(const char *arg); 49#endif 50 51static unsigned long long MAX_MEMORY = 512ull << 20; 52 53struct octeon_boot_descriptor *octeon_boot_desc_ptr; 54 55struct cvmx_bootinfo *octeon_bootinfo; 56EXPORT_SYMBOL(octeon_bootinfo); 57 58static unsigned long long RESERVE_LOW_MEM = 0ull; 59#ifdef CONFIG_KEXEC 60#ifdef CONFIG_SMP 61/* 62 * Wait for relocation code is prepared and send 63 * secondary CPUs to spin until kernel is relocated. 64 */ 65static void octeon_kexec_smp_down(void *ignored) 66{ 67 int cpu = smp_processor_id(); 68 69 local_irq_disable(); 70 set_cpu_online(cpu, false); 71 while (!atomic_read(&kexec_ready_to_reboot)) 72 cpu_relax(); 73 74 asm volatile ( 75 " sync \n" 76 " synci ($0) \n"); 77 78 relocated_kexec_smp_wait(NULL); 79} 80#endif 81 82#define OCTEON_DDR0_BASE (0x0ULL) 83#define OCTEON_DDR0_SIZE (0x010000000ULL) 84#define OCTEON_DDR1_BASE (0x410000000ULL) 85#define OCTEON_DDR1_SIZE (0x010000000ULL) 86#define OCTEON_DDR2_BASE (0x020000000ULL) 87#define OCTEON_DDR2_SIZE (0x3e0000000ULL) 88#define OCTEON_MAX_PHY_MEM_SIZE (16*1024*1024*1024ULL) 89 90static struct kimage *kimage_ptr; 91 92static void kexec_bootmem_init(uint64_t mem_size, uint32_t low_reserved_bytes) 93{ 94 int64_t addr; 95 struct cvmx_bootmem_desc *bootmem_desc; 96 97 bootmem_desc = cvmx_bootmem_get_desc(); 98 99 if (mem_size > OCTEON_MAX_PHY_MEM_SIZE) { 100 mem_size = OCTEON_MAX_PHY_MEM_SIZE; 101 pr_err("Error: requested memory too large," 102 "truncating to maximum size\n"); 103 } 104 105 bootmem_desc->major_version = CVMX_BOOTMEM_DESC_MAJ_VER; 106 bootmem_desc->minor_version = CVMX_BOOTMEM_DESC_MIN_VER; 107 108 addr = (OCTEON_DDR0_BASE + RESERVE_LOW_MEM + low_reserved_bytes); 109 bootmem_desc->head_addr = 0; 110 111 if (mem_size <= OCTEON_DDR0_SIZE) { 112 __cvmx_bootmem_phy_free(addr, 113 mem_size - RESERVE_LOW_MEM - 114 low_reserved_bytes, 0); 115 return; 116 } 117 118 __cvmx_bootmem_phy_free(addr, 119 OCTEON_DDR0_SIZE - RESERVE_LOW_MEM - 120 low_reserved_bytes, 0); 121 122 mem_size -= OCTEON_DDR0_SIZE; 123 124 if (mem_size > OCTEON_DDR1_SIZE) { 125 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, OCTEON_DDR1_SIZE, 0); 126 __cvmx_bootmem_phy_free(OCTEON_DDR2_BASE, 127 mem_size - OCTEON_DDR1_SIZE, 0); 128 } else 129 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, mem_size, 0); 130} 131 132static int octeon_kexec_prepare(struct kimage *image) 133{ 134 int i; 135 char *bootloader = "kexec"; 136 137 octeon_boot_desc_ptr->argc = 0; 138 for (i = 0; i < image->nr_segments; i++) { 139 if (!strncmp(bootloader, (char *)image->segment[i].buf, 140 strlen(bootloader))) { 141 /* 142 * convert command line string to array 143 * of parameters (as bootloader does). 144 */ 145 int argc = 0, offt; 146 char *str = (char *)image->segment[i].buf; 147 char *ptr = strchr(str, ' '); 148 while (ptr && (OCTEON_ARGV_MAX_ARGS > argc)) { 149 *ptr = '\0'; 150 if (ptr[1] != ' ') { 151 offt = (int)(ptr - str + 1); 152 octeon_boot_desc_ptr->argv[argc] = 153 image->segment[i].mem + offt; 154 argc++; 155 } 156 ptr = strchr(ptr + 1, ' '); 157 } 158 octeon_boot_desc_ptr->argc = argc; 159 break; 160 } 161 } 162 163 /* 164 * Information about segments will be needed during pre-boot memory 165 * initialization. 166 */ 167 kimage_ptr = image; 168 return 0; 169} 170 171static void octeon_generic_shutdown(void) 172{ 173 int i; 174#ifdef CONFIG_SMP 175 int cpu; 176#endif 177 struct cvmx_bootmem_desc *bootmem_desc; 178 void *named_block_array_ptr; 179 180 bootmem_desc = cvmx_bootmem_get_desc(); 181 named_block_array_ptr = 182 cvmx_phys_to_ptr(bootmem_desc->named_block_array_addr); 183 184#ifdef CONFIG_SMP 185 /* disable watchdogs */ 186 for_each_online_cpu(cpu) 187 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); 188#else 189 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 190#endif 191 if (kimage_ptr != kexec_crash_image) { 192 memset(named_block_array_ptr, 193 0x0, 194 CVMX_BOOTMEM_NUM_NAMED_BLOCKS * 195 sizeof(struct cvmx_bootmem_named_block_desc)); 196 /* 197 * Mark all memory (except low 0x100000 bytes) as free. 198 * It is the same thing that bootloader does. 199 */ 200 kexec_bootmem_init(octeon_bootinfo->dram_size*1024ULL*1024ULL, 201 0x100000); 202 /* 203 * Allocate all segments to avoid their corruption during boot. 204 */ 205 for (i = 0; i < kimage_ptr->nr_segments; i++) 206 cvmx_bootmem_alloc_address( 207 kimage_ptr->segment[i].memsz + 2*PAGE_SIZE, 208 kimage_ptr->segment[i].mem - PAGE_SIZE, 209 PAGE_SIZE); 210 } else { 211 /* 212 * Do not mark all memory as free. Free only named sections 213 * leaving the rest of memory unchanged. 214 */ 215 struct cvmx_bootmem_named_block_desc *ptr = 216 (struct cvmx_bootmem_named_block_desc *) 217 named_block_array_ptr; 218 219 for (i = 0; i < bootmem_desc->named_block_num_blocks; i++) 220 if (ptr[i].size) 221 cvmx_bootmem_free_named(ptr[i].name); 222 } 223 kexec_args[2] = 1UL; /* running on octeon_main_processor */ 224 kexec_args[3] = (unsigned long)octeon_boot_desc_ptr; 225#ifdef CONFIG_SMP 226 secondary_kexec_args[2] = 0UL; /* running on secondary cpu */ 227 secondary_kexec_args[3] = (unsigned long)octeon_boot_desc_ptr; 228#endif 229} 230 231static void octeon_shutdown(void) 232{ 233 octeon_generic_shutdown(); 234#ifdef CONFIG_SMP 235 smp_call_function(octeon_kexec_smp_down, NULL, 0); 236 smp_wmb(); 237 while (num_online_cpus() > 1) { 238 cpu_relax(); 239 mdelay(1); 240 } 241#endif 242} 243 244static void octeon_crash_shutdown(struct pt_regs *regs) 245{ 246 octeon_generic_shutdown(); 247 default_machine_crash_shutdown(regs); 248} 249 250#endif /* CONFIG_KEXEC */ 251 252#ifdef CONFIG_CAVIUM_RESERVE32 253uint64_t octeon_reserve32_memory; 254EXPORT_SYMBOL(octeon_reserve32_memory); 255#endif 256 257#ifdef CONFIG_KEXEC 258/* crashkernel cmdline parameter is parsed _after_ memory setup 259 * we also parse it here (workaround for EHB5200) */ 260static uint64_t crashk_size, crashk_base; 261#endif 262 263static int octeon_uart; 264 265extern asmlinkage void handle_int(void); 266 267/** 268 * Return non zero if we are currently running in the Octeon simulator 269 * 270 * Returns 271 */ 272int octeon_is_simulation(void) 273{ 274 return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM; 275} 276EXPORT_SYMBOL(octeon_is_simulation); 277 278/** 279 * Return true if Octeon is in PCI Host mode. This means 280 * Linux can control the PCI bus. 281 * 282 * Returns Non zero if Octeon in host mode. 283 */ 284int octeon_is_pci_host(void) 285{ 286#ifdef CONFIG_PCI 287 return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST; 288#else 289 return 0; 290#endif 291} 292 293/** 294 * Get the clock rate of Octeon 295 * 296 * Returns Clock rate in HZ 297 */ 298uint64_t octeon_get_clock_rate(void) 299{ 300 struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get(); 301 302 return sysinfo->cpu_clock_hz; 303} 304EXPORT_SYMBOL(octeon_get_clock_rate); 305 306static u64 octeon_io_clock_rate; 307 308u64 octeon_get_io_clock_rate(void) 309{ 310 return octeon_io_clock_rate; 311} 312EXPORT_SYMBOL(octeon_get_io_clock_rate); 313 314 315/** 316 * Write to the LCD display connected to the bootbus. This display 317 * exists on most Cavium evaluation boards. If it doesn't exist, then 318 * this function doesn't do anything. 319 * 320 * @s: String to write 321 */ 322void octeon_write_lcd(const char *s) 323{ 324 if (octeon_bootinfo->led_display_base_addr) { 325 void __iomem *lcd_address = 326 ioremap_nocache(octeon_bootinfo->led_display_base_addr, 327 8); 328 int i; 329 for (i = 0; i < 8; i++, s++) { 330 if (*s) 331 iowrite8(*s, lcd_address + i); 332 else 333 iowrite8(' ', lcd_address + i); 334 } 335 iounmap(lcd_address); 336 } 337} 338 339/** 340 * Return the console uart passed by the bootloader 341 * 342 * Returns uart (0 or 1) 343 */ 344int octeon_get_boot_uart(void) 345{ 346 int uart; 347#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL 348 uart = 1; 349#else 350 uart = (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ? 351 1 : 0; 352#endif 353 return uart; 354} 355 356/** 357 * Get the coremask Linux was booted on. 358 * 359 * Returns Core mask 360 */ 361int octeon_get_boot_coremask(void) 362{ 363 return octeon_boot_desc_ptr->core_mask; 364} 365 366/** 367 * Check the hardware BIST results for a CPU 368 */ 369void octeon_check_cpu_bist(void) 370{ 371 const int coreid = cvmx_get_core_num(); 372 unsigned long long mask; 373 unsigned long long bist_val; 374 375 /* Check BIST results for COP0 registers */ 376 mask = 0x1f00000000ull; 377 bist_val = read_octeon_c0_icacheerr(); 378 if (bist_val & mask) 379 pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n", 380 coreid, bist_val); 381 382 bist_val = read_octeon_c0_dcacheerr(); 383 if (bist_val & 1) 384 pr_err("Core%d L1 Dcache parity error: " 385 "CacheErr(dcache) = 0x%llx\n", 386 coreid, bist_val); 387 388 mask = 0xfc00000000000000ull; 389 bist_val = read_c0_cvmmemctl(); 390 if (bist_val & mask) 391 pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n", 392 coreid, bist_val); 393 394 write_octeon_c0_dcacheerr(0); 395} 396 397/** 398 * Reboot Octeon 399 * 400 * @command: Command to pass to the bootloader. Currently ignored. 401 */ 402static void octeon_restart(char *command) 403{ 404 /* Disable all watchdogs before soft reset. They don't get cleared */ 405#ifdef CONFIG_SMP 406 int cpu; 407 for_each_online_cpu(cpu) 408 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); 409#else 410 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 411#endif 412 413 mb(); 414 while (1) 415 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1); 416} 417 418 419/** 420 * Permanently stop a core. 421 * 422 * @arg: Ignored. 423 */ 424static void octeon_kill_core(void *arg) 425{ 426 if (octeon_is_simulation()) 427 /* A break instruction causes the simulator stop a core */ 428 asm volatile ("break" ::: "memory"); 429 430 local_irq_disable(); 431 /* Disable watchdog on this core. */ 432 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 433 /* Spin in a low power mode. */ 434 while (true) 435 asm volatile ("wait" ::: "memory"); 436} 437 438 439/** 440 * Halt the system 441 */ 442static void octeon_halt(void) 443{ 444 smp_call_function(octeon_kill_core, NULL, 0); 445 446 switch (octeon_bootinfo->board_type) { 447 case CVMX_BOARD_TYPE_NAO38: 448 /* Driving a 1 to GPIO 12 shuts off this board */ 449 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1); 450 cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000); 451 break; 452 default: 453 octeon_write_lcd("PowerOff"); 454 break; 455 } 456 457 octeon_kill_core(NULL); 458} 459 460static char __read_mostly octeon_system_type[80]; 461 462static int __init init_octeon_system_type(void) 463{ 464 snprintf(octeon_system_type, sizeof(octeon_system_type), "%s (%s)", 465 cvmx_board_type_to_string(octeon_bootinfo->board_type), 466 octeon_model_get_string(read_c0_prid())); 467 468 return 0; 469} 470early_initcall(init_octeon_system_type); 471 472/** 473 * Return a string representing the system type 474 * 475 * Returns 476 */ 477const char *octeon_board_type_string(void) 478{ 479 return octeon_system_type; 480} 481 482const char *get_system_type(void) 483 __attribute__ ((alias("octeon_board_type_string"))); 484 485void octeon_user_io_init(void) 486{ 487 union octeon_cvmemctl cvmmemctl; 488 union cvmx_iob_fau_timeout fau_timeout; 489 union cvmx_pow_nw_tim nm_tim; 490 491 /* Get the current settings for CP0_CVMMEMCTL_REG */ 492 cvmmemctl.u64 = read_c0_cvmmemctl(); 493 /* R/W If set, marked write-buffer entries time out the same 494 * as as other entries; if clear, marked write-buffer entries 495 * use the maximum timeout. */ 496 cvmmemctl.s.dismarkwblongto = 1; 497 /* R/W If set, a merged store does not clear the write-buffer 498 * entry timeout state. */ 499 cvmmemctl.s.dismrgclrwbto = 0; 500 /* R/W Two bits that are the MSBs of the resultant CVMSEG LM 501 * word location for an IOBDMA. The other 8 bits come from the 502 * SCRADDR field of the IOBDMA. */ 503 cvmmemctl.s.iobdmascrmsb = 0; 504 /* R/W If set, SYNCWS and SYNCS only order marked stores; if 505 * clear, SYNCWS and SYNCS only order unmarked 506 * stores. SYNCWSMARKED has no effect when DISSYNCWS is 507 * set. */ 508 cvmmemctl.s.syncwsmarked = 0; 509 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */ 510 cvmmemctl.s.dissyncws = 0; 511 /* R/W If set, no stall happens on write buffer full. */ 512 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) 513 cvmmemctl.s.diswbfst = 1; 514 else 515 cvmmemctl.s.diswbfst = 0; 516 /* R/W If set (and SX set), supervisor-level loads/stores can 517 * use XKPHYS addresses with <48>==0 */ 518 cvmmemctl.s.xkmemenas = 0; 519 520 /* R/W If set (and UX set), user-level loads/stores can use 521 * XKPHYS addresses with VA<48>==0 */ 522 cvmmemctl.s.xkmemenau = 0; 523 524 /* R/W If set (and SX set), supervisor-level loads/stores can 525 * use XKPHYS addresses with VA<48>==1 */ 526 cvmmemctl.s.xkioenas = 0; 527 528 /* R/W If set (and UX set), user-level loads/stores can use 529 * XKPHYS addresses with VA<48>==1 */ 530 cvmmemctl.s.xkioenau = 0; 531 532 /* R/W If set, all stores act as SYNCW (NOMERGE must be set 533 * when this is set) RW, reset to 0. */ 534 cvmmemctl.s.allsyncw = 0; 535 536 /* R/W If set, no stores merge, and all stores reach the 537 * coherent bus in order. */ 538 cvmmemctl.s.nomerge = 0; 539 /* R/W Selects the bit in the counter used for DID time-outs 0 540 * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is 541 * between 1x and 2x this interval. For example, with 542 * DIDTTO=3, expiration interval is between 16K and 32K. */ 543 cvmmemctl.s.didtto = 0; 544 /* R/W If set, the (mem) CSR clock never turns off. */ 545 cvmmemctl.s.csrckalwys = 0; 546 /* R/W If set, mclk never turns off. */ 547 cvmmemctl.s.mclkalwys = 0; 548 /* R/W Selects the bit in the counter used for write buffer 549 * flush time-outs (WBFLT+11) is the bit position in an 550 * internal counter used to determine expiration. The write 551 * buffer expires between 1x and 2x this interval. For 552 * example, with WBFLT = 0, a write buffer expires between 2K 553 * and 4K cycles after the write buffer entry is allocated. */ 554 cvmmemctl.s.wbfltime = 0; 555 /* R/W If set, do not put Istream in the L2 cache. */ 556 cvmmemctl.s.istrnol2 = 0; 557 558 /* 559 * R/W The write buffer threshold. As per erratum Core-14752 560 * for CN63XX, a sc/scd might fail if the write buffer is 561 * full. Lowering WBTHRESH greatly lowers the chances of the 562 * write buffer ever being full and triggering the erratum. 563 */ 564 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) 565 cvmmemctl.s.wbthresh = 4; 566 else 567 cvmmemctl.s.wbthresh = 10; 568 569 /* R/W If set, CVMSEG is available for loads/stores in 570 * kernel/debug mode. */ 571#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 572 cvmmemctl.s.cvmsegenak = 1; 573#else 574 cvmmemctl.s.cvmsegenak = 0; 575#endif 576 /* R/W If set, CVMSEG is available for loads/stores in 577 * supervisor mode. */ 578 cvmmemctl.s.cvmsegenas = 0; 579 /* R/W If set, CVMSEG is available for loads/stores in user 580 * mode. */ 581 cvmmemctl.s.cvmsegenau = 0; 582 /* R/W Size of local memory in cache blocks, 54 (6912 bytes) 583 * is max legal value. */ 584 cvmmemctl.s.lmemsz = CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE; 585 586 write_c0_cvmmemctl(cvmmemctl.u64); 587 588 if (smp_processor_id() == 0) 589 pr_notice("CVMSEG size: %d cache lines (%d bytes)\n", 590 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE, 591 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128); 592 593 /* Set a default for the hardware timeouts */ 594 fau_timeout.u64 = 0; 595 fau_timeout.s.tout_val = 0xfff; 596 /* Disable tagwait FAU timeout */ 597 fau_timeout.s.tout_enb = 0; 598 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64); 599 600 nm_tim.u64 = 0; 601 /* 4096 cycles */ 602 nm_tim.s.nw_tim = 3; 603 cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64); 604 605 write_octeon_c0_icacheerr(0); 606 write_c0_derraddr1(0); 607} 608 609/** 610 * Early entry point for arch setup 611 */ 612void __init prom_init(void) 613{ 614 struct cvmx_sysinfo *sysinfo; 615 const char *arg; 616 char *p; 617 int i; 618 int argc; 619#ifdef CONFIG_CAVIUM_RESERVE32 620 int64_t addr = -1; 621#endif 622 /* 623 * The bootloader passes a pointer to the boot descriptor in 624 * $a3, this is available as fw_arg3. 625 */ 626 octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3; 627 octeon_bootinfo = 628 cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr); 629 cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr)); 630 631 sysinfo = cvmx_sysinfo_get(); 632 memset(sysinfo, 0, sizeof(*sysinfo)); 633 sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20; 634 sysinfo->phy_mem_desc_ptr = 635 cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr); 636 sysinfo->core_mask = octeon_bootinfo->core_mask; 637 sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr; 638 sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz; 639 sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2; 640 sysinfo->board_type = octeon_bootinfo->board_type; 641 sysinfo->board_rev_major = octeon_bootinfo->board_rev_major; 642 sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor; 643 memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base, 644 sizeof(sysinfo->mac_addr_base)); 645 sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count; 646 memcpy(sysinfo->board_serial_number, 647 octeon_bootinfo->board_serial_number, 648 sizeof(sysinfo->board_serial_number)); 649 sysinfo->compact_flash_common_base_addr = 650 octeon_bootinfo->compact_flash_common_base_addr; 651 sysinfo->compact_flash_attribute_base_addr = 652 octeon_bootinfo->compact_flash_attribute_base_addr; 653 sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr; 654 sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz; 655 sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags; 656 657 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { 658 /* I/O clock runs at a different rate than the CPU. */ 659 union cvmx_mio_rst_boot rst_boot; 660 rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT); 661 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul; 662 } else { 663 octeon_io_clock_rate = sysinfo->cpu_clock_hz; 664 } 665 666 /* 667 * Only enable the LED controller if we're running on a CN38XX, CN58XX, 668 * or CN56XX. The CN30XX and CN31XX don't have an LED controller. 669 */ 670 if (!octeon_is_simulation() && 671 octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) { 672 cvmx_write_csr(CVMX_LED_EN, 0); 673 cvmx_write_csr(CVMX_LED_PRT, 0); 674 cvmx_write_csr(CVMX_LED_DBG, 0); 675 cvmx_write_csr(CVMX_LED_PRT_FMT, 0); 676 cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32); 677 cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32); 678 cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0); 679 cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0); 680 cvmx_write_csr(CVMX_LED_EN, 1); 681 } 682#ifdef CONFIG_CAVIUM_RESERVE32 683 /* 684 * We need to temporarily allocate all memory in the reserve32 685 * region. This makes sure the kernel doesn't allocate this 686 * memory when it is getting memory from the 687 * bootloader. Later, after the memory allocations are 688 * complete, the reserve32 will be freed. 689 * 690 * Allocate memory for RESERVED32 aligned on 2MB boundary. This 691 * is in case we later use hugetlb entries with it. 692 */ 693 addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20, 694 0, 0, 2 << 20, 695 "CAVIUM_RESERVE32", 0); 696 if (addr < 0) 697 pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n"); 698 else 699 octeon_reserve32_memory = addr; 700#endif 701 702#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2 703 if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) { 704 pr_info("Skipping L2 locking due to reduced L2 cache size\n"); 705 } else { 706 uint32_t __maybe_unused ebase = read_c0_ebase() & 0x3ffff000; 707#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB 708 /* TLB refill */ 709 cvmx_l2c_lock_mem_region(ebase, 0x100); 710#endif 711#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION 712 /* General exception */ 713 cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80); 714#endif 715#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT 716 /* Interrupt handler */ 717 cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80); 718#endif 719#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT 720 cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100); 721 cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80); 722#endif 723#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY 724 cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480); 725#endif 726 } 727#endif 728 729 octeon_check_cpu_bist(); 730 731 octeon_uart = octeon_get_boot_uart(); 732 733#ifdef CONFIG_SMP 734 octeon_write_lcd("LinuxSMP"); 735#else 736 octeon_write_lcd("Linux"); 737#endif 738 739 octeon_setup_delays(); 740 741 /* 742 * BIST should always be enabled when doing a soft reset. L2 743 * Cache locking for instance is not cleared unless BIST is 744 * enabled. Unfortunately due to a chip errata G-200 for 745 * Cn38XX and CN31XX, BIST msut be disabled on these parts. 746 */ 747 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) || 748 OCTEON_IS_MODEL(OCTEON_CN31XX)) 749 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0); 750 else 751 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1); 752 753 /* Default to 64MB in the simulator to speed things up */ 754 if (octeon_is_simulation()) 755 MAX_MEMORY = 64ull << 20; 756 757 arg = strstr(arcs_cmdline, "mem="); 758 if (arg) { 759 MAX_MEMORY = memparse(arg + 4, &p); 760 if (MAX_MEMORY == 0) 761 MAX_MEMORY = 32ull << 30; 762 if (*p == '@') 763 RESERVE_LOW_MEM = memparse(p + 1, &p); 764 } 765 766 arcs_cmdline[0] = 0; 767 argc = octeon_boot_desc_ptr->argc; 768 for (i = 0; i < argc; i++) { 769 const char *arg = 770 cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]); 771 if ((strncmp(arg, "MEM=", 4) == 0) || 772 (strncmp(arg, "mem=", 4) == 0)) { 773 MAX_MEMORY = memparse(arg + 4, &p); 774 if (MAX_MEMORY == 0) 775 MAX_MEMORY = 32ull << 30; 776 if (*p == '@') 777 RESERVE_LOW_MEM = memparse(p + 1, &p); 778#ifdef CONFIG_KEXEC 779 } else if (strncmp(arg, "crashkernel=", 12) == 0) { 780 crashk_size = memparse(arg+12, &p); 781 if (*p == '@') 782 crashk_base = memparse(p+1, &p); 783 strcat(arcs_cmdline, " "); 784 strcat(arcs_cmdline, arg); 785 /* 786 * To do: switch parsing to new style, something like: 787 * parse_crashkernel(arg, sysinfo->system_dram_size, 788 * &crashk_size, &crashk_base); 789 */ 790#endif 791 } else if (strlen(arcs_cmdline) + strlen(arg) + 1 < 792 sizeof(arcs_cmdline) - 1) { 793 strcat(arcs_cmdline, " "); 794 strcat(arcs_cmdline, arg); 795 } 796 } 797 798 if (strstr(arcs_cmdline, "console=") == NULL) { 799#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL 800 strcat(arcs_cmdline, " console=ttyS0,115200"); 801#else 802 if (octeon_uart == 1) 803 strcat(arcs_cmdline, " console=ttyS1,115200"); 804 else 805 strcat(arcs_cmdline, " console=ttyS0,115200"); 806#endif 807 } 808 809 mips_hpt_frequency = octeon_get_clock_rate(); 810 811 octeon_init_cvmcount(); 812 813 _machine_restart = octeon_restart; 814 _machine_halt = octeon_halt; 815 816#ifdef CONFIG_KEXEC 817 _machine_kexec_shutdown = octeon_shutdown; 818 _machine_crash_shutdown = octeon_crash_shutdown; 819 _machine_kexec_prepare = octeon_kexec_prepare; 820#endif 821 822 octeon_user_io_init(); 823 register_smp_ops(&octeon_smp_ops); 824} 825 826/* Exclude a single page from the regions obtained in plat_mem_setup. */ 827#ifndef CONFIG_CRASH_DUMP 828static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size) 829{ 830 if (addr > *mem && addr < *mem + *size) { 831 u64 inc = addr - *mem; 832 add_memory_region(*mem, inc, BOOT_MEM_RAM); 833 *mem += inc; 834 *size -= inc; 835 } 836 837 if (addr == *mem && *size > PAGE_SIZE) { 838 *mem += PAGE_SIZE; 839 *size -= PAGE_SIZE; 840 } 841} 842#endif /* CONFIG_CRASH_DUMP */ 843 844void __init plat_mem_setup(void) 845{ 846 uint64_t mem_alloc_size; 847 uint64_t total; 848 uint64_t crashk_end; 849#ifndef CONFIG_CRASH_DUMP 850 int64_t memory; 851 uint64_t kernel_start; 852 uint64_t kernel_size; 853#endif 854 855 total = 0; 856 crashk_end = 0; 857 858 /* 859 * The Mips memory init uses the first memory location for 860 * some memory vectors. When SPARSEMEM is in use, it doesn't 861 * verify that the size is big enough for the final 862 * vectors. Making the smallest chuck 4MB seems to be enough 863 * to consistently work. 864 */ 865 mem_alloc_size = 4 << 20; 866 if (mem_alloc_size > MAX_MEMORY) 867 mem_alloc_size = MAX_MEMORY; 868 869/* Crashkernel ignores bootmem list. It relies on mem=X@Y option */ 870#ifdef CONFIG_CRASH_DUMP 871 add_memory_region(RESERVE_LOW_MEM, MAX_MEMORY, BOOT_MEM_RAM); 872 total += MAX_MEMORY; 873#else 874#ifdef CONFIG_KEXEC 875 if (crashk_size > 0) { 876 add_memory_region(crashk_base, crashk_size, BOOT_MEM_RAM); 877 crashk_end = crashk_base + crashk_size; 878 } 879#endif 880 /* 881 * When allocating memory, we want incrementing addresses from 882 * bootmem_alloc so the code in add_memory_region can merge 883 * regions next to each other. 884 */ 885 cvmx_bootmem_lock(); 886 while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX) 887 && (total < MAX_MEMORY)) { 888 memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 889 __pa_symbol(&__init_end), -1, 890 0x100000, 891 CVMX_BOOTMEM_FLAG_NO_LOCKING); 892 if (memory >= 0) { 893 u64 size = mem_alloc_size; 894#ifdef CONFIG_KEXEC 895 uint64_t end; 896#endif 897 898 /* 899 * exclude a page at the beginning and end of 900 * the 256MB PCIe 'hole' so the kernel will not 901 * try to allocate multi-page buffers that 902 * span the discontinuity. 903 */ 904 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE, 905 &memory, &size); 906 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE + 907 CVMX_PCIE_BAR1_PHYS_SIZE, 908 &memory, &size); 909#ifdef CONFIG_KEXEC 910 end = memory + mem_alloc_size; 911 912 /* 913 * This function automatically merges address regions 914 * next to each other if they are received in 915 * incrementing order 916 */ 917 if (memory < crashk_base && end > crashk_end) { 918 /* region is fully in */ 919 add_memory_region(memory, 920 crashk_base - memory, 921 BOOT_MEM_RAM); 922 total += crashk_base - memory; 923 add_memory_region(crashk_end, 924 end - crashk_end, 925 BOOT_MEM_RAM); 926 total += end - crashk_end; 927 continue; 928 } 929 930 if (memory >= crashk_base && end <= crashk_end) 931 /* 932 * Entire memory region is within the new 933 * kernel's memory, ignore it. 934 */ 935 continue; 936 937 if (memory > crashk_base && memory < crashk_end && 938 end > crashk_end) { 939 /* 940 * Overlap with the beginning of the region, 941 * reserve the beginning. 942 */ 943 mem_alloc_size -= crashk_end - memory; 944 memory = crashk_end; 945 } else if (memory < crashk_base && end > crashk_base && 946 end < crashk_end) 947 /* 948 * Overlap with the beginning of the region, 949 * chop of end. 950 */ 951 mem_alloc_size -= end - crashk_base; 952#endif 953 add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM); 954 total += mem_alloc_size; 955 /* Recovering mem_alloc_size */ 956 mem_alloc_size = 4 << 20; 957 } else { 958 break; 959 } 960 } 961 cvmx_bootmem_unlock(); 962 /* Add the memory region for the kernel. */ 963 kernel_start = (unsigned long) _text; 964 kernel_size = _end - _text; 965 966 /* Adjust for physical offset. */ 967 kernel_start &= ~0xffffffff80000000ULL; 968 add_memory_region(kernel_start, kernel_size, BOOT_MEM_RAM); 969#endif /* CONFIG_CRASH_DUMP */ 970 971#ifdef CONFIG_CAVIUM_RESERVE32 972 /* 973 * Now that we've allocated the kernel memory it is safe to 974 * free the reserved region. We free it here so that builtin 975 * drivers can use the memory. 976 */ 977 if (octeon_reserve32_memory) 978 cvmx_bootmem_free_named("CAVIUM_RESERVE32"); 979#endif /* CONFIG_CAVIUM_RESERVE32 */ 980 981 if (total == 0) 982 panic("Unable to allocate memory from " 983 "cvmx_bootmem_phy_alloc"); 984} 985 986/* 987 * Emit one character to the boot UART. Exported for use by the 988 * watchdog timer. 989 */ 990int prom_putchar(char c) 991{ 992 uint64_t lsrval; 993 994 /* Spin until there is room */ 995 do { 996 lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart)); 997 } while ((lsrval & 0x20) == 0); 998 999 /* Write the byte */ 1000 cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull); 1001 return 1; 1002} 1003EXPORT_SYMBOL(prom_putchar); 1004 1005void prom_free_prom_memory(void) 1006{ 1007 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) { 1008 /* Check for presence of Core-14449 fix. */ 1009 u32 insn; 1010 u32 *foo; 1011 1012 foo = &insn; 1013 1014 asm volatile("# before" : : : "memory"); 1015 prefetch(foo); 1016 asm volatile( 1017 ".set push\n\t" 1018 ".set noreorder\n\t" 1019 "bal 1f\n\t" 1020 "nop\n" 1021 "1:\tlw %0,-12($31)\n\t" 1022 ".set pop\n\t" 1023 : "=r" (insn) : : "$31", "memory"); 1024 1025 if ((insn >> 26) != 0x33) 1026 panic("No PREF instruction at Core-14449 probe point."); 1027 1028 if (((insn >> 16) & 0x1f) != 28) 1029 panic("Core-14449 WAR not in place (%04x).\n" 1030 "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).", insn); 1031 } 1032} 1033 1034int octeon_prune_device_tree(void); 1035 1036extern const char __dtb_octeon_3xxx_begin; 1037extern const char __dtb_octeon_68xx_begin; 1038void __init device_tree_init(void) 1039{ 1040 const void *fdt; 1041 bool do_prune; 1042 1043 if (octeon_bootinfo->minor_version >= 3 && octeon_bootinfo->fdt_addr) { 1044 fdt = phys_to_virt(octeon_bootinfo->fdt_addr); 1045 if (fdt_check_header(fdt)) 1046 panic("Corrupt Device Tree passed to kernel."); 1047 do_prune = false; 1048 } else if (OCTEON_IS_MODEL(OCTEON_CN68XX)) { 1049 fdt = &__dtb_octeon_68xx_begin; 1050 do_prune = true; 1051 } else { 1052 fdt = &__dtb_octeon_3xxx_begin; 1053 do_prune = true; 1054 } 1055 1056 initial_boot_params = (void *)fdt; 1057 1058 if (do_prune) { 1059 octeon_prune_device_tree(); 1060 pr_info("Using internal Device Tree.\n"); 1061 } else { 1062 pr_info("Using passed Device Tree.\n"); 1063 } 1064 unflatten_and_copy_device_tree(); 1065} 1066 1067static int __initdata disable_octeon_edac_p; 1068 1069static int __init disable_octeon_edac(char *str) 1070{ 1071 disable_octeon_edac_p = 1; 1072 return 0; 1073} 1074early_param("disable_octeon_edac", disable_octeon_edac); 1075 1076static char *edac_device_names[] = { 1077 "octeon_l2c_edac", 1078 "octeon_pc_edac", 1079}; 1080 1081static int __init edac_devinit(void) 1082{ 1083 struct platform_device *dev; 1084 int i, err = 0; 1085 int num_lmc; 1086 char *name; 1087 1088 if (disable_octeon_edac_p) 1089 return 0; 1090 1091 for (i = 0; i < ARRAY_SIZE(edac_device_names); i++) { 1092 name = edac_device_names[i]; 1093 dev = platform_device_register_simple(name, -1, NULL, 0); 1094 if (IS_ERR(dev)) { 1095 pr_err("Registation of %s failed!\n", name); 1096 err = PTR_ERR(dev); 1097 } 1098 } 1099 1100 num_lmc = OCTEON_IS_MODEL(OCTEON_CN68XX) ? 4 : 1101 (OCTEON_IS_MODEL(OCTEON_CN56XX) ? 2 : 1); 1102 for (i = 0; i < num_lmc; i++) { 1103 dev = platform_device_register_simple("octeon_lmc_edac", 1104 i, NULL, 0); 1105 if (IS_ERR(dev)) { 1106 pr_err("Registation of octeon_lmc_edac %d failed!\n", i); 1107 err = PTR_ERR(dev); 1108 } 1109 } 1110 1111 return err; 1112} 1113device_initcall(edac_devinit); 1114 1115static void __initdata *octeon_dummy_iospace; 1116 1117static int __init octeon_no_pci_init(void) 1118{ 1119 /* 1120 * Initially assume there is no PCI. The PCI/PCIe platform code will 1121 * later re-initialize these to correct values if they are present. 1122 */ 1123 octeon_dummy_iospace = vzalloc(IO_SPACE_LIMIT); 1124 set_io_port_base((unsigned long)octeon_dummy_iospace); 1125 ioport_resource.start = MAX_RESOURCE; 1126 ioport_resource.end = 0; 1127 return 0; 1128} 1129core_initcall(octeon_no_pci_init); 1130 1131static int __init octeon_no_pci_release(void) 1132{ 1133 /* 1134 * Release the allocated memory if a real IO space is there. 1135 */ 1136 if ((unsigned long)octeon_dummy_iospace != mips_io_port_base) 1137 vfree(octeon_dummy_iospace); 1138 return 0; 1139} 1140late_initcall(octeon_no_pci_release); 1141