/drivers/net/ethernet/altera/ |
H A D | altera_utils.c | 20 void tse_set_bit(void __iomem *ioaddr, size_t offs, u32 bit_mask) argument 22 u32 value = csrrd32(ioaddr, offs); 24 csrwr32(value, ioaddr, offs); 27 void tse_clear_bit(void __iomem *ioaddr, size_t offs, u32 bit_mask) argument 29 u32 value = csrrd32(ioaddr, offs); 31 csrwr32(value, ioaddr, offs); 34 int tse_bit_is_set(void __iomem *ioaddr, size_t offs, u32 bit_mask) argument 36 u32 value = csrrd32(ioaddr, offs); 40 int tse_bit_is_clear(void __iomem *ioaddr, size_t offs, u32 bit_mask) argument 42 u32 value = csrrd32(ioaddr, off [all...] |
/drivers/net/ethernet/dec/tulip/ |
H A D | pnic.c | 22 void __iomem *ioaddr = tp->base_addr; local 23 u32 phy_reg = ioread32(ioaddr + 0xB8); 33 iowrite32(0x32 | (dev->if_port & 1), ioaddr + CSR12); 35 iowrite32(0x1F868, ioaddr + 0xB8); 55 void __iomem *ioaddr = tp->base_addr; local 56 int phy_reg = ioread32(ioaddr + 0xB8); 61 if (ioread32(ioaddr + CSR5) & TPLnkFail) { 62 iowrite32((ioread32(ioaddr + CSR7) & ~TPLnkFail) | TPLnkPass, ioaddr + CSR7); 70 iowrite32(tp->csr6, ioaddr 91 void __iomem *ioaddr = tp->base_addr; local [all...] |
H A D | pnic2.c | 83 void __iomem *ioaddr = tp->base_addr; local 88 ioread32(ioaddr + CSR12)); 99 void __iomem *ioaddr = tp->base_addr; local 108 csr14 = (ioread32(ioaddr + CSR14) & 0xfff0ee39); 135 tp->csr6 = ioread32(ioaddr + CSR6); 153 iowrite32(csr14, ioaddr + CSR14); 154 iowrite32(tp->csr6, ioaddr + CSR6); 163 csr12 = (ioread32(ioaddr + CSR12) & 0xffff8fff); 165 iowrite32(csr12, ioaddr + CSR12); 173 void __iomem *ioaddr local [all...] |
H A D | timer.c | 22 void __iomem *ioaddr = tp->base_addr; local 23 u32 csr12 = ioread32(ioaddr + CSR12); 30 ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR6), 31 csr12, ioread32(ioaddr + CSR13), 32 ioread32(ioaddr + CSR14), ioread32(ioaddr + CSR15)); 49 ioread32(ioaddr + CSR6), 128 tulip_tx_timeout_complete(tp, ioaddr); 144 void __iomem *ioaddr local [all...] |
H A D | 21142.c | 33 void __iomem *ioaddr = tp->base_addr; local 34 int csr12 = ioread32(ioaddr + CSR12); 37 int csr14 = ioread32(ioaddr + CSR14); 79 iowrite32(0, ioaddr + CSR13); 80 iowrite32(0x0003FFFF, ioaddr + CSR14); 81 iowrite16(t21142_csr15[dev->if_port], ioaddr + CSR15); 82 iowrite32(t21142_csr13[dev->if_port], ioaddr + CSR13); 87 iowrite32(0, ioaddr + CSR13); 88 iowrite32(0x0003FFFF, ioaddr + CSR14); 89 iowrite16(8, ioaddr 114 void __iomem *ioaddr = tp->base_addr; local 142 void __iomem *ioaddr = tp->base_addr; local [all...] |
/drivers/net/ethernet/stmicro/stmmac/ |
H A D | stmmac_hwtstamp.c | 31 static void stmmac_config_hw_tstamping(void __iomem *ioaddr, u32 data) argument 33 writel(data, ioaddr + PTP_TCR); 36 static void stmmac_config_sub_second_increment(void __iomem *ioaddr) argument 38 u32 value = readl(ioaddr + PTP_TCR); 51 writel(data, ioaddr + PTP_SSIR); 54 static int stmmac_init_systime(void __iomem *ioaddr, u32 sec, u32 nsec) argument 59 writel(sec, ioaddr + PTP_STSUR); 60 writel(nsec, ioaddr + PTP_STNSUR); 62 value = readl(ioaddr + PTP_TCR); 64 writel(value, ioaddr 79 stmmac_config_addend(void __iomem *ioaddr, u32 addend) argument 103 stmmac_adjust_systime(void __iomem *ioaddr, u32 sec, u32 nsec, int add_sub) argument 130 stmmac_get_systime(void __iomem *ioaddr) argument [all...] |
H A D | dwmac1000_dma.c | 33 static int dwmac1000_dma_init(void __iomem *ioaddr, int pbl, int fb, int mb, argument 36 u32 value = readl(ioaddr + DMA_BUS_MODE); 41 writel(value, ioaddr + DMA_BUS_MODE); 44 if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET)) 80 writel(value, ioaddr + DMA_BUS_MODE); 99 writel(burst_len, ioaddr + DMA_AXI_BUS_MODE); 102 writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA); 107 writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR); 108 writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR); 113 static void dwmac1000_dma_operation_mode(void __iomem *ioaddr, in argument 163 dwmac1000_dump_dma_regs(void __iomem *ioaddr) argument 177 dwmac1000_get_hw_feature(void __iomem *ioaddr) argument 182 dwmac1000_rx_watchdog(void __iomem *ioaddr, u32 riwt) argument [all...] |
H A D | dwmac100_dma.c | 35 static int dwmac100_dma_init(void __iomem *ioaddr, int pbl, int fb, int mb, argument 38 u32 value = readl(ioaddr + DMA_BUS_MODE); 43 writel(value, ioaddr + DMA_BUS_MODE); 46 if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET)) 55 ioaddr + DMA_BUS_MODE); 58 writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA); 63 writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR); 64 writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR); 74 static void dwmac100_dma_operation_mode(void __iomem *ioaddr, int txmode, argument 77 u32 csr6 = readl(ioaddr 89 dwmac100_dump_dma_regs(void __iomem *ioaddr) argument 105 dwmac100_dma_diagnostic_fr(void *data, struct stmmac_extra_stats *x, void __iomem *ioaddr) argument [all...] |
H A D | dwmac100_core.c | 37 void __iomem *ioaddr = hw->pcsr; local 38 u32 value = readl(ioaddr + MAC_CONTROL); 40 writel((value | MAC_CORE_INIT), ioaddr + MAC_CONTROL); 43 writel(ETH_P_8021Q, ioaddr + MAC_VLAN1); 49 void __iomem *ioaddr = hw->pcsr; local 52 "\t----------------------------------------------\n", ioaddr); 54 readl(ioaddr + MAC_CONTROL)); 56 readl(ioaddr + MAC_ADDR_HIGH)); 58 readl(ioaddr + MAC_ADDR_LOW)); 60 MAC_HASH_HIGH, readl(ioaddr 86 void __iomem *ioaddr = hw->pcsr; local 94 void __iomem *ioaddr = hw->pcsr; local 101 void __iomem *ioaddr = (void __iomem *)dev->base_addr; local 150 void __iomem *ioaddr = hw->pcsr; local 176 dwmac100_setup(void __iomem *ioaddr) argument [all...] |
/drivers/isdn/hardware/eicon/ |
H A D | s_bri.c | 44 byte __iomem *addrHi, *addrLo, *ioaddr; local 57 ioaddr = Port + DATA; 60 for (i = 0; i < 0x100; Xlog[i++] = inppw(ioaddr)); 75 xlogDesc.cnt = inppw(ioaddr); 78 xlogDesc.out = inppw(ioaddr); 90 Xlog[i++] = inppw(ioaddr);
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/drivers/scsi/ |
H A D | zorro7xx.c | 80 unsigned long board, ioaddr; local 86 ioaddr = zdd->offset; 88 ioaddr = board + zdd->offset; 104 if (ioaddr > 0x01000000) 105 hostdata->base = ioremap(ioaddr, zorro_resource_len(z)); 107 hostdata->base = ZTWO_VADDR(ioaddr); 127 host->base = ioaddr; 144 if (ioaddr > 0x01000000)
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/drivers/ata/ |
H A D | pata_platform.c | 57 static void pata_platform_setup_port(struct ata_ioports *ioaddr, argument 61 ioaddr->data_addr = ioaddr->cmd_addr + (ATA_REG_DATA << shift); 62 ioaddr->error_addr = ioaddr->cmd_addr + (ATA_REG_ERR << shift); 63 ioaddr->feature_addr = ioaddr->cmd_addr + (ATA_REG_FEATURE << shift); 64 ioaddr->nsect_addr = ioaddr->cmd_addr + (ATA_REG_NSECT << shift); 65 ioaddr [all...] |
H A D | pata_cs5520.c | 130 struct ata_ioports *ioaddr; local 186 ioaddr = &host->ports[0]->ioaddr; 187 ioaddr->cmd_addr = iomap[0]; 188 ioaddr->ctl_addr = iomap[1]; 189 ioaddr->altstatus_addr = iomap[1]; 190 ioaddr->bmdma_addr = iomap[4]; 191 ata_sff_std_ports(ioaddr); 197 ioaddr = &host->ports[1]->ioaddr; [all...] |
H A D | pata_hpt3x3.c | 100 void __iomem *mmio = ap->ioaddr.bmdma_addr; 119 u8 r = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); 121 iowrite8(r, ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); 235 struct ata_ioports *ioaddr = &ap->ioaddr; local 237 ioaddr->cmd_addr = base + offset_cmd[i]; 238 ioaddr->altstatus_addr = 239 ioaddr->ctl_addr = base + offset_ctl[i]; 240 ioaddr->scr_addr = NULL; 241 ata_sff_std_ports(ioaddr); [all...] |
H A D | pata_imx.c | 78 static void pata_imx_setup_port(struct ata_ioports *ioaddr) argument 81 ioaddr->data_addr = ioaddr->cmd_addr + (ATA_REG_DATA << 2); 82 ioaddr->error_addr = ioaddr->cmd_addr + (ATA_REG_ERR << 2); 83 ioaddr->feature_addr = ioaddr->cmd_addr + (ATA_REG_FEATURE << 2); 84 ioaddr->nsect_addr = ioaddr->cmd_addr + (ATA_REG_NSECT << 2); 85 ioaddr [all...] |
H A D | pata_ixp4xx_cf.c | 50 void __iomem *mmio = ap->ioaddr.data_addr; 103 struct ata_ioports *ioaddr = &ap->ioaddr; local 107 ioaddr->cmd_addr = data->cs0; 108 ioaddr->altstatus_addr = data->cs1 + 0x06; 109 ioaddr->ctl_addr = data->cs1 + 0x06; 111 ata_sff_std_ports(ioaddr); 119 *(unsigned long *)&ioaddr->data_addr ^= 0x02; 120 *(unsigned long *)&ioaddr->cmd_addr ^= 0x03; 121 *(unsigned long *)&ioaddr [all...] |
H A D | sata_uli.c | 152 struct ata_ioports *ioaddr; local 192 ioaddr = &host->ports[2]->ioaddr; 193 ioaddr->cmd_addr = iomap[0] + 8; 194 ioaddr->altstatus_addr = 195 ioaddr->ctl_addr = (void __iomem *) 197 ioaddr->bmdma_addr = iomap[4] + 16; 199 ata_sff_std_ports(ioaddr); 207 ioaddr = &host->ports[3]->ioaddr; [all...] |
/drivers/gpio/ |
H A D | gpio-moxart.c | 54 void __iomem *ioaddr = gc->base + GPIO_DATA_OUT; local 55 u32 reg = readl(ioaddr); 62 writel(reg, ioaddr); 79 void __iomem *ioaddr = gc->base + GPIO_PIN_DIRECTION; local 81 writel(readl(ioaddr) & ~BIT(offset), ioaddr); 89 void __iomem *ioaddr = gc->base + GPIO_PIN_DIRECTION; local 92 writel(readl(ioaddr) | BIT(offset), ioaddr);
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/drivers/gpu/drm/bochs/ |
H A D | bochs_hw.c | 54 unsigned long addr, size, mem, ioaddr, iosize; local 64 ioaddr = pci_resource_start(pdev, 2); 66 bochs->mmio = ioremap(ioaddr, iosize); 72 ioaddr = VBE_DISPI_IOPORT_INDEX; 74 if (!request_region(ioaddr, iosize, "bochs-drm")) { 118 ioaddr);
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/drivers/net/arcnet/ |
H A D | com20020-isa.c | 53 int ioaddr; local 60 ioaddr = dev->base_addr; 61 if (!ioaddr) { 66 if (!request_region(ioaddr, ARCNET_TOTAL_SIZE, "arcnet (COM20020)")) { 68 ioaddr, ioaddr + ARCNET_TOTAL_SIZE - 1); 72 BUGMSG(D_NORMAL, "IO address %x empty\n", ioaddr); 116 release_region(ioaddr, ARCNET_TOTAL_SIZE);
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H A D | com20020_cs.c | 56 int ioaddr = dev->base_addr; local 60 for (count = ioaddr; count < ioaddr + 16; count++) 201 int ioaddr; local 218 for (ioaddr = 0x100; ioaddr < 0x400; ioaddr += 0x10) 220 link->resource[0]->start = ioaddr; 235 ioaddr = dev->base_addr = link->resource[0]->start; 236 dev_dbg(&link->dev, "got ioaddr 305 int ioaddr = dev->base_addr; local [all...] |
H A D | com20020-pci.c | 73 int i, ioaddr, ret; local 102 ioaddr = pci_resource_start(pdev, cm->bar) + cm->offset; 104 r = devm_request_region(&pdev->dev, ioaddr, cm->size, 108 ioaddr, ioaddr + cm->size - 1); 117 outb(0x00, ioaddr + 1); 118 inb(ioaddr + 1); 120 dev->base_addr = ioaddr; 132 pr_err("IO address %Xh is empty!\n", ioaddr);
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H A D | com20020.c | 63 int ioaddr = dev->base_addr, ofs = 512 * bufnum + offset; local 77 int ioaddr = dev->base_addr, ofs = 512 * bufnum + offset; local 91 int ioaddr = dev->base_addr, status; local 120 outb(0x42, ioaddr + BUS_ALIGN*7); 132 outb(inb(ioaddr + BUS_ALIGN*8), ioaddr + BUS_ALIGN*7); 154 int ioaddr = dev->base_addr; local 180 int ioaddr = dev->base_addr; local 196 dev->dev_addr[0] = inb(ioaddr + BUS_ALIGN*8); /* FIXME: do this some other way! */ 223 dev->base_addr = ioaddr; 257 u_int ioaddr = dev->base_addr; local 301 u_int ioaddr = dev->base_addr; local 309 u_int ioaddr = dev->base_addr; local 316 u_int ioaddr = dev->base_addr; local 324 int ioaddr = dev->base_addr; local 341 int ioaddr = dev->base_addr; local [all...] |
/drivers/net/ethernet/samsung/sxgbe/ |
H A D | sxgbe_mtl.c | 23 static void sxgbe_mtl_init(void __iomem *ioaddr, unsigned int etsalg, argument 28 reg_val = readl(ioaddr + SXGBE_MTL_OP_MODE_REG); 43 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG); 53 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG); 57 static void sxgbe_mtl_dma_dm_rxqueue(void __iomem *ioaddr) argument 59 writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP0_REG); 60 writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP1_REG); 61 writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP2_REG); 64 static void sxgbe_mtl_set_txfifosize(void __iomem *ioaddr, int queue_num, argument 71 reg_val = readl(ioaddr 76 sxgbe_mtl_set_rxfifosize(void __iomem *ioaddr, int queue_num, int queue_fifo) argument 88 sxgbe_mtl_enable_txqueue(void __iomem *ioaddr, int queue_num) argument 97 sxgbe_mtl_disable_txqueue(void __iomem *ioaddr, int queue_num) argument 106 sxgbe_mtl_fc_active(void __iomem *ioaddr, int queue_num, int threshold) argument 118 sxgbe_mtl_fc_enable(void __iomem *ioaddr, int queue_num) argument 127 sxgbe_mtl_fc_deactive(void __iomem *ioaddr, int queue_num, int threshold) argument 139 sxgbe_mtl_fep_enable(void __iomem *ioaddr, int queue_num) argument 149 sxgbe_mtl_fep_disable(void __iomem *ioaddr, int queue_num) argument 159 sxgbe_mtl_fup_enable(void __iomem *ioaddr, int queue_num) argument 169 sxgbe_mtl_fup_disable(void __iomem *ioaddr, int queue_num) argument 180 sxgbe_set_tx_mtl_mode(void __iomem *ioaddr, int queue_num, int tx_mode) argument 211 sxgbe_set_rx_mtl_mode(void __iomem *ioaddr, int queue_num, int rx_mode) argument [all...] |
H A D | sxgbe_mdio.c | 32 static int sxgbe_mdio_busy_wait(void __iomem *ioaddr, unsigned int mii_data) argument 37 if (!(readl(ioaddr + mii_data) & SXGBE_MII_BUSY)) 52 writel(reg, sp->ioaddr + sp->hw->mii.data); 63 writel(reg, sp->ioaddr + sp->hw->mii.addr); 73 writel(1 << phyaddr, sp->ioaddr + SXGBE_MDIO_CLAUSE22_PORT_REG); 77 writel(reg, sp->ioaddr + sp->hw->mii.addr); 88 rc = sxgbe_mdio_busy_wait(sp->ioaddr, mii->data); 102 return sxgbe_mdio_busy_wait(sp->ioaddr, mii->data); 122 return readl(priv->ioaddr + priv->hw->mii.data) & 0xffff;
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