/arch/x86/mm/kmemcheck/ |
H A D | pte.c | 10 unsigned int level; local 12 pte = lookup_address(address, &level); 15 if (level != PG_LEVEL_4K)
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/arch/x86/boot/ |
H A D | cpuflags.h | 8 int level; /* Family, or 64 for x86-64 */ member in struct:cpu_features
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H A D | cpu.c | 23 static char *cpu_name(int level) argument 27 if (level == 64) { 30 if (level == 15) 31 level = 6; 32 sprintf(buf, "i%d86", level);
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H A D | cpucheck.c | 97 * *cpu_level is set to the current CPU level; *req_level to the required 98 * level. x86-64 is considered level 64 for this purpose. 107 cpu.level = 3; 110 cpu.level = 4; 116 cpu.level = 64; 154 u32 level = 1; local 159 : "+a" (level), "=d" (cpu.flags[0]) 166 is_intel() && cpu.level == 6 && 182 *cpu_level_ptr = cpu.level; [all...] |
/arch/arm/include/asm/ |
H A D | ftrace.h | 48 static inline void *return_address(unsigned int level) argument
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/arch/arm/kernel/ |
H A D | return_address.c | 20 unsigned int level; member in struct:return_address_data 28 if (!data->level) { 33 --data->level; 38 void *return_address(unsigned int level) argument 44 data.level = level + 2; 54 if (!data.level)
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/arch/arm64/kernel/ |
H A D | return_address.c | 18 unsigned int level; member in struct:return_address_data 26 if (!data->level) { 30 --data->level; 35 void *return_address(unsigned int level) argument 40 data.level = level + 2; 49 if (!data.level)
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/arch/arm/mach-pxa/ |
H A D | reset.c | 25 int init_gpio_reset(int gpio, int output, int level) argument 36 rc = gpio_direction_output(gpio, level);
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/arch/blackfin/include/asm/ |
H A D | ftrace.h | 34 extern inline void *return_address(unsigned int level) argument 39 if (level == 0) 43 endstack = (unsigned long *)PAGE_ALIGN((unsigned long)&level); 46 (fp + 1) < endstack && current_level < level) { 62 extern inline void *return_address(unsigned int level) argument
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/arch/frv/kernel/ |
H A D | irq.c | 116 int level; local 118 for (level = 1; level <= 14; level++) 119 irq_set_chip_and_handler(level, &frv_cpu_pic, 127 * - all others are high-level
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/arch/powerpc/platforms/52xx/ |
H A D | lite5200.c | 129 u8 level = 0; /* wakeup on low level */ local 130 mpc52xx_set_wakeup_gpio(pin, level);
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/arch/s390/include/uapi/asm/ |
H A D | debug.h | 22 unsigned long long level:3; member in struct:__debug_entry::__anon2555::__anon2556
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/arch/mips/loongson/common/ |
H A D | gpio.c | 95 unsigned gpio, int level) 103 gpio_set_value(gpio, level); 94 ls2f_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int level) argument
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/arch/sh/boards/mach-x3proto/ |
H A D | ilsel.c | 29 * With each level being relative to an ilsel_source_t. 35 * ILSEL level map, in descending order from the highest level down. 39 * to the interrupt level, the level map is carefully managed to ensure a 88 * available interrupt level. Callers should take care to order callsites 115 * ilsel_enable_fixed - Enable an ILSEL set at a fixed interrupt level 117 * @level: Interrupt level (1 - 15) 119 * Enables a given ILSEL source at a fixed interrupt level 125 ilsel_enable_fixed(ilsel_source_t set, unsigned int level) argument [all...] |
/arch/x86/kernel/cpu/ |
H A D | scattered.c | 16 u32 level; member in struct:cpuid_bit 59 /* Verify that the level is valid */ 60 max_level = cpuid_eax(cb->level & 0xffff0000); 61 if (max_level < cb->level || 62 max_level > (cb->level | 0xffff)) 65 cpuid_count(cb->level, cb->sub_leaf, ®s[CR_EAX],
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/arch/arm/mach-gemini/ |
H A D | irq.c | 76 unsigned int i, mode = 0, level = 0; local 91 level |= 1 << i; 104 __raw_writel(level, IRQ_TLEVEL(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
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/arch/arm/mach-omap2/ |
H A D | sdrc2xxx.c | 76 * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC. 82 u32 omap2xxx_sdrc_reprogram(u32 level, u32 force) argument 88 if ((curr_perf_level == level) && !force) 91 if (level == CORE_CLK_SRC_DPLL) 93 else if (level == CORE_CLK_SRC_DPLL_X2) 109 omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type); 110 curr_perf_level = level;
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/arch/avr32/mach-at32ap/ |
H A D | intc.c | 58 asmlinkage void do_IRQ(int level, struct pt_regs *regs) argument 70 irq = intc_readl(&intc0, INTCAUSE0 - 4 * level); 74 * Clear all interrupt level masks so that we may handle 119 * Initialize all interrupts to level 0 (lowest priority). The 120 * priority level may be changed by calling
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/arch/mn10300/include/asm/ |
H A D | irqflags.h | 22 * - level 0 - kernel debugger 23 * - level 1 - virtual serial DMA (if present) 24 * - level 5 - normal interrupt priority 25 * - level 6 - timer interrupt 166 static inline void arch_local_change_intr_mask_level(unsigned long level) argument 172 : "i"(~EPSW_IM), "i"(EPSW_IE | level) 210 #define LOCAL_CHANGE_INTR_MASK_LEVEL(level) \ 212 or EPSW_IE|(level),epsw
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/arch/powerpc/platforms/powernv/ |
H A D | opal-hmi.c | 43 const char *level, *sevstr, *error_info; local 67 level = KERN_INFO; 71 level = KERN_WARNING; 75 level = KERN_ERR; 80 level = KERN_ERR; 86 level, sevstr, 92 printk("%s Error detail: %s\n", level, error_info); 93 printk("%s HMER: %016llx\n", level, be64_to_cpu(hmi_evt->hmer)); 96 printk("%s TFMR: %016llx\n", level,
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/arch/sh/boards/mach-dreamcast/ |
H A D | irq.c | 108 __u32 emr, esr, status, level; local 113 level = 0; 116 level = 1; 119 level = 2; 124 emr = EMR_BASE + (level << 4) + (level << 2); 125 esr = ESR_BASE + (level << 2); 134 irq = HW_EVENT_IRQ_BASE + j + (level << 5);
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/arch/xtensa/kernel/ |
H A D | stacktrace.c | 110 unsigned long return_address(unsigned level) argument 113 .skip = level + 1,
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/arch/arm/include/asm/xen/ |
H A D | page.h | 84 static inline pte_t *lookup_address(unsigned long address, unsigned int *level) argument
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/arch/arm/mach-msm/ |
H A D | board-trout-mmc.c | 75 int level; member in struct:mmc_vdd_xlat 131 printk("%s: Setting level to %u\n", 132 __func__, mmc_vdd_table[i].level); 135 mmc_vdd_table[i].level); 138 "%s: Error setting vreg level (%d)\n",
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/arch/mips/sgi-ip27/ |
H A D | ip27-irq-pci.c | 68 int level; local 70 level = find_first_zero_bit(hub->irq_alloc_mask, LEVELS_PER_SLICE); 71 if (level >= LEVELS_PER_SLICE) 74 __set_bit(level, hub->irq_alloc_mask); 75 si->level_to_irq[level] = irq; 77 return level; 95 panic("Could not identify cpu/level for irq %d", irq);
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