Searched defs:rate (Results 1 - 25 of 99) sorted by relevance

1234

/arch/arm/plat-versatile/
H A Dsched-clock.c37 void __init versatile_sched_clock_init(void __iomem *reg, unsigned long rate) argument
40 sched_clock_register(versatile_read_sched_clock, 32, rate);
H A Dclock.c34 return clk->rate;
38 long clk_round_rate(struct clk *clk, unsigned long rate) argument
42 ret = clk->ops->round(clk, rate);
47 int clk_set_rate(struct clk *clk, unsigned long rate) argument
51 ret = clk->ops->set(clk, rate);
56 long icst_clk_round(struct clk *clk, unsigned long rate) argument
59 vco = icst_hz_to_vco(clk->params, rate);
64 int icst_clk_set(struct clk *clk, unsigned long rate) argument
68 vco = icst_hz_to_vco(clk->params, rate);
69 clk->rate
[all...]
/arch/arm/mach-omap2/
H A Domap2-restart.c36 u32 rate; local
38 rate = clk_get_rate(reset_sys_ck);
39 clk_set_rate(reset_virt_prcm_set_ck, rate);
H A Dclock3xxx.c41 int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate, argument
50 pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
54 return omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
79 * Switch the MPU rate if specified on cmdline. We cannot do this
H A Dclkt34xx_dpll3m2.c33 * CORE DPLL (DPLL3) M2 divider rate programming functions
42 * @rate: rounded target rate
44 * Program the DPLL M2 divider with the rounded target rate. Returns
47 int omap3_core_dpll_m2_set_rate(struct clk_hw *hw, unsigned long rate, argument
60 if (!clk || !rate)
63 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
64 if (validrate != rate)
69 if (rate > clkrate)
70 sdrcrate <<= ((rate / clkrat
[all...]
H A Dclkt2xxx_dpllcore.c46 * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
48 * Returns the CORE_CLK rate. CORE_CLK can have one of three rate
49 * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
74 * Uses the current prcm set to tell if a rate is valid.
75 * You can go slower, but not faster within a given rate set.
111 int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate, argument
123 if ((rate == (cur_rate / 2)) && (mult == 2)) {
125 } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
127 } else if (rate !
[all...]
/arch/powerpc/sysdev/qe_lib/
H A Dusb.c23 int qe_usb_clock_set(enum qe_clock clk, int rate) argument
46 qe_setbrg(clk, rate, 1);
/arch/arm/mach-omap1/
H A Dopp.h19 unsigned long rate; member in struct:mpu_rate
/arch/arm/mach-versatile/include/mach/
H A Dclkdev.h7 unsigned long rate; member in struct:clk
/arch/m68k/include/asm/
H A Dmcfclk.h19 unsigned long rate; member in struct:clk
36 .rate = clk_rate, \
46 .rate = clk_rate, \
/arch/mips/ralink/
H A Dclk.c21 unsigned long rate; member in struct:clk
24 void ralink_clk_add(const char *dev, unsigned long rate) argument
34 clk->rate = rate;
55 return clk->rate;
/arch/arm/mach-imx/
H A Dclk.c41 const char *name, unsigned long rate)
47 clk = imx_clk_fixed(name, rate);
40 imx_obtain_fixed_clock( const char *name, unsigned long rate) argument
H A Dclk-fixup-div.c51 static long clk_fixup_div_round_rate(struct clk_hw *hw, unsigned long rate, argument
56 return fixup_div->ops->round_rate(&fixup_div->divider.hw, rate, prate);
59 static int clk_fixup_div_set_rate(struct clk_hw *hw, unsigned long rate, argument
68 divider = parent_rate / rate;
H A Dclk-pfd.c71 static long clk_pfd_round_rate(struct clk_hw *hw, unsigned long rate, argument
77 tmp = tmp * 18 + rate / 2;
78 do_div(tmp, rate);
91 static int clk_pfd_set_rate(struct clk_hw *hw, unsigned long rate, argument
98 tmp = tmp * 18 + rate / 2;
99 do_div(tmp, rate);
H A Dclk-pllv1.c46 unsigned long rate; local
51 * Get the resulting clock rate from a PLL register value and the input
81 rate = parent_rate * 2;
82 rate /= pd + 1;
84 ll = (unsigned long long)rate * mfn_abs;
91 ll = (rate * mfi) + ll;
/arch/arm/mach-lpc32xx/
H A Dclock.h25 u32 rate; member in struct:clk
/arch/arm/mach-mmp/
H A Dclock.c81 unsigned long rate; local
84 rate = clk->ops->getrate(clk);
86 rate = clk->rate;
88 return rate;
92 int clk_set_rate(struct clk *clk, unsigned long rate) argument
99 ret = clk->ops->setrate(clk, rate);
H A Dclock.h24 unsigned long rate; member in struct:clk
35 .rate = _rate, \
43 .rate = _rate, \
51 .rate = _rate, \
59 .rate = _rate, \
/arch/arm/mach-pxa/
H A Dclock.c46 unsigned long rate; local
48 rate = clk->rate;
50 rate = clk->ops->getrate(clk);
52 return rate;
56 int clk_set_rate(struct clk *clk, unsigned long rate) argument
63 ret = clk->ops->setrate(clk, rate);
H A Dclock.h13 unsigned long rate; member in struct:clk
41 .rate = _rate, \
48 .rate = _rate, \
64 .rate = _rate, \
/arch/arm/mach-footbridge/
H A Ddc21285-timer.c118 unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16); local
120 clocksource_register_hz(&cksrc_dc21285, rate);
125 clockevents_config_and_register(ce, rate, 0x4, 0xffffff);
135 unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16); local
141 sched_clock_register(footbridge_read_sched_clock, 24, rate);
/arch/blackfin/mach-common/
H A Dclock.h8 unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
9 int (*set_rate)(struct clk *clk, unsigned long rate);
16 unsigned long rate; member in struct:clk
/arch/mips/include/asm/
H A Dclock.h16 int (*set_rate) (struct clk *clk, unsigned long rate, int algo_id);
17 long (*round_rate) (struct clk *clk, unsigned long rate);
31 unsigned long rate; member in struct:clk
/arch/mips/kernel/
H A Dcevt-ds1287.c35 u8 rate; local
39 rate = 0x9;
42 rate = 0x8;
45 rate = 0x6;
51 CMOS_WRITE(RTC_REF_CLCK_32KHZ | rate, RTC_REG_A);
/arch/arm/mach-mvebu/
H A Dplatsmp.c52 unsigned long rate; local
60 rate = clk_get_rate(cpu_clk);
62 /* set all the other CPU clk to the same rate than the boot CPU */
69 clk_set_rate(cpu_clk, rate);

Completed in 416 milliseconds

1234