/arch/blackfin/mach-bf561/include/mach/ |
H A D | blackfin.h | 24 #define bfin_write_FIO_FLAG_D(val) bfin_write_FIO0_FLAG_D(val) 26 #define bfin_write_FIO_DIR(val) bfin_write_FIO0_DIR(val) 28 #define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val) 33 #define bfin_write_SIC_IMASK(x, val) bfin_write32(__SIC_MUX(SIC_IMASK0, x), val) 35 #define bfin_write_SICB_IMASK(x, val) bfin_write32(__SIC_MUX(SICB_IMASK0, x), val) [all...] |
/arch/s390/include/asm/ |
H A D | percpu.h | 28 #define arch_this_cpu_to_op_simple(pcp, val, op) \ 38 new__ = old__ op (val); \ 45 #define this_cpu_add_1(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +) 46 #define this_cpu_add_2(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +) 47 #define this_cpu_add_return_1(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +) 48 #define this_cpu_add_return_2(pcp, val) arch_this_cpu_to_op_simple(pcp, val, [all...] |
/arch/arm/nwfpe/ |
H A D | fpmodule.inl | 32 unsigned int val = regs->uregs[nReg]; 34 val -= 4; 35 return val; 39 writeRegister(const unsigned int nReg, const unsigned long val) 42 regs->uregs[nReg] = val; 50 static inline void writeCPSR(const unsigned long val) 52 writeRegister(REG_CPSR, val); 64 static inline void writeConditionCodes(const unsigned long val) 73 regs->ARM_cpsr = rval | (val & CC_MASK);
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/arch/arm/mach-davinci/ |
H A D | pm.c | 42 unsigned val; local 47 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL); 48 val &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN); 49 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL); 54 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL); 55 val |= PLLCTL_PLLPWRDN; 56 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL); 60 val = __raw_readl(pdata->deepsleep_reg); 61 val &= ~DEEPSLEEP_SLEEPCOUNT_MASK, 62 val | [all...] |
/arch/parisc/include/asm/ |
H A D | special_insns.h | 21 static inline void set_eiem(unsigned long val) argument 23 mtctl(val, 15); 35 #define mtsp(val, cr) \ 36 { if (__builtin_constant_p(val) && ((val) == 0)) \ 41 : "r" (val), "i" (cr) : "memory"); }
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/arch/mips/include/asm/ |
H A D | mipsmtregs.h | 20 #define write_c0_mvpcontrol(val) __write_32bit_c0_register($0, 1, val) 26 #define write_c0_vpecontrol(val) __write_32bit_c0_register($1, 1, val) 29 #define write_c0_vpeconf0(val) __write_32bit_c0_register($1, 2, val) 32 #define write_c0_vpeconf1(val) __write_32bit_c0_register($1, 3, val) 35 #define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val) [all...] |
H A D | mipsregs.h | 807 #define write_r10k_perf_cntr(counter,val) \ 812 : "r" (val), "i" (counter)); \ 826 #define write_r10k_perf_cntl(counter,val) \ 831 : "r" (val), "i" (counter)); \ 910 #define __write_ulong_c0_register(reg, sel, val) \ 913 __write_32bit_c0_register(reg, sel, val); \ 915 __write_64bit_c0_register(reg, sel, val); \ 969 #define __write_64bit_c0_split(source, sel, val) \ 983 : : "r" (val)); \ 993 : : "r" (val)); \ [all...] |
/arch/powerpc/platforms/cell/ |
H A D | celleb_scc_uhc.c | 32 static inline int uhc_clkctrl_ready(u32 val) argument 35 return((val & mask) == mask); 47 u32 val = 0; local 64 val |= SCC_UHC_F48MCKLEN; 65 out_be32(uhc_clkctrl, val); 66 val |= SCC_UHC_PHY_SUSPEND_SEL; 67 out_be32(uhc_clkctrl, val); 69 val |= SCC_UHC_PHYEN; 70 out_be32(uhc_clkctrl, val); 74 val | [all...] |
H A D | celleb_scc_epci.c | 83 u32 val; local 89 val = in_be32(reg); 91 if (val & (PCI_STATUS_REC_MASTER_ABORT << 16)) { 93 (val & 0xffff) | (PCI_STATUS_REC_MASTER_ABORT << 16)); 100 val = in_be32(reg) & 0xffff; 101 val |= SCC_EPCI_VCSR_FRE; 102 out_be32(reg, val); 133 unsigned int devfn, int where, int size, u32 *val) 153 *val = in_8(addr); 156 *val 132 celleb_epci_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) argument 192 celleb_epci_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) argument 256 u32 val; local [all...] |
/arch/arm/mach-iop13xx/ |
H A D | irq.c | 34 u32 val; local 35 asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val)); 36 return val; 38 static void write_intctl_0(u32 val) argument 40 asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val)); 47 u32 val; local 48 asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val)); 49 return val; 51 static void write_intctl_1(u32 val) argument 53 asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val)); 60 u32 val; local 64 write_intctl_2(u32 val) argument 73 u32 val; local 77 write_intctl_3(u32 val) argument 84 write_intstr_0(u32 val) argument 91 write_intstr_1(u32 val) argument 98 write_intstr_2(u32 val) argument 105 write_intstr_3(u32 val) argument 112 write_intbase(u32 val) argument 119 write_intsize(u32 val) argument [all...] |
/arch/cris/include/arch-v32/arch/hwregs/ |
H A D | reg_rdwr.h | 13 #define REG_WRITE(type, addr, val) \ 14 do { *((volatile type *) (addr)) = (val); } while(0)
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/arch/mips/pci/ |
H A D | pci-lantiq.h | 14 unsigned int devfn, int where, int size, u32 *val); 16 unsigned int devfn, int where, int size, u32 val);
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/arch/x86/include/asm/ |
H A D | debugreg.h | 22 unsigned long val = 0; /* Damn you, gcc! */ local 26 asm("mov %%db0, %0" :"=r" (val)); 29 asm("mov %%db1, %0" :"=r" (val)); 32 asm("mov %%db2, %0" :"=r" (val)); 35 asm("mov %%db3, %0" :"=r" (val)); 38 asm("mov %%db6, %0" :"=r" (val)); 41 asm("mov %%db7, %0" :"=r" (val)); 46 return val;
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/arch/tile/include/asm/ |
H A D | spinlock_64.h | 30 static inline u32 arch_spin_current(u32 val) argument 32 return val >> __ARCH_SPIN_CURRENT_SHIFT; 39 static inline u32 arch_spin_next(u32 val) argument 41 return val & __ARCH_SPIN_NEXT_MASK; 47 u32 val = lock->lock; local 48 return arch_spin_current(val) != arch_spin_next(val); 60 void arch_spin_lock_slow(arch_spinlock_t *lock, u32 val); 68 u32 val = __insn_fetchadd4(&lock->lock, 1); local 69 u32 ticket = val 90 arch_write_val_locked(int val) argument 117 u32 val = __insn_fetchaddgez4(&rw->lock, 1); local 126 u32 val = __insn_fetchor4(&rw->lock, __WRITE_LOCK_BIT); local 150 u32 val = __insn_fetchor4(&rw->lock, __WRITE_LOCK_BIT); local [all...] |
/arch/arm/mach-imx/ |
H A D | cpu-imx27.c | 36 u32 val; local 42 val = __raw_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR 45 mx27_cpu_partnumber = (int)((val >> 12) & 0xFFFF); 47 switch (val >> 28) {
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/arch/avr32/include/uapi/asm/ |
H A D | swab.h | 22 static inline __attribute_const__ __u16 __arch_swab16(__u16 val) argument 24 return __builtin_bswap_16(val); 28 static inline __attribute_const__ __u32 __arch_swab32(__u32 val) argument 30 return __builtin_bswap_32(val);
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/arch/ia64/include/asm/ |
H A D | patch.h | 17 extern void ia64_patch (u64 insn_addr, u64 mask, u64 val); /* patch any insn slot */ 18 extern void ia64_patch_imm64 (u64 insn_addr, u64 val); /* patch "movl" w/abs. value*/ 19 extern void ia64_patch_imm60 (u64 insn_addr, u64 val); /* patch "brl" w/ip-rel value */ 23 extern void ia64_patch_phys_stack_reg(unsigned long val);
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/arch/mips/include/asm/mach-ralink/ |
H A D | ralink_regs.h | 19 static inline void rt_sysc_w32(u32 val, unsigned reg) argument 21 __raw_writel(val, rt_sysc_membase + reg); 29 static inline void rt_memc_w32(u32 val, unsigned reg) argument 31 __raw_writel(val, rt_memc_membase + reg);
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/arch/sh/include/asm/ |
H A D | cmpxchg-grb.h | 4 static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val) argument 19 "+r" (val) /* inhibit r15 overloading */ 26 static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val) argument 41 "+r" (val) /* inhibit r15 overloading */
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/arch/arm/mach-iop33x/ |
H A D | irq.c | 25 static void intctl0_write(u32 val) argument 27 asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); 30 static void intctl1_write(u32 val) argument 32 asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val)); 35 static void intstr0_write(u32 val) argument 37 asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val)); 40 static void intstr1_write(u32 val) argument 42 asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val)); 45 static void intbase_write(u32 val) argument 47 asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val)); 50 intsize_write(u32 val) argument [all...] |
/arch/mn10300/kernel/ |
H A D | io.c | 22 unsigned long val; local 25 memcpy(&val, buf, 4); 26 outl(val, addr);
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/arch/powerpc/include/asm/ |
H A D | kvm_booke.h | 37 static inline void kvmppc_set_gpr(struct kvm_vcpu *vcpu, int num, ulong val) argument 39 vcpu->arch.gpr[num] = val; 47 static inline void kvmppc_set_cr(struct kvm_vcpu *vcpu, u32 val) argument 49 vcpu->arch.cr = val; 57 static inline void kvmppc_set_xer(struct kvm_vcpu *vcpu, u32 val) argument 59 vcpu->arch.xer = val; 73 static inline void kvmppc_set_ctr(struct kvm_vcpu *vcpu, ulong val) argument 75 vcpu->arch.ctr = val; 83 static inline void kvmppc_set_lr(struct kvm_vcpu *vcpu, ulong val) argument 85 vcpu->arch.lr = val; 93 kvmppc_set_pc(struct kvm_vcpu *vcpu, ulong val) argument [all...] |
/arch/powerpc/sysdev/ |
H A D | grackle.c | 32 unsigned int val; local 35 val = in_le32(bp->cfg_data); 36 val = enable? (val | GRACKLE_PICR1_STG) : 37 (val & ~GRACKLE_PICR1_STG); 39 out_le32(bp->cfg_data, val); 45 unsigned int val; local 48 val = in_le32(bp->cfg_data); 49 val = enable? (val | GRACKLE_PICR1_LOOPSNOO [all...] |
/arch/arm/mach-hisi/ |
H A D | hotplug.c | 78 u32 val = 0; local 91 val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN 93 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS); 95 val |= CPU0_HPM_SRST_REQ_EN; 96 writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN); 105 val = readl_relaxed(ctrl_base + SCPERCTRL0); 106 val &= ~(CPU0_WFI_MASK_CFG << cpu); 107 writel_relaxed(val, ctrl_base + SCPERCTRL0); 110 val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN 112 writel_relaxed(val << cp 182 u32 val = 0; local [all...] |
/arch/alpha/include/asm/ |
H A D | fpu.h | 37 wrfpcr(unsigned long val) argument 47 : "=&r"(tmp) : "r"(val)); 54 : "=m"(tmp) : "m"(val)); 71 extern void alpha_write_fp_reg (unsigned long reg, unsigned long val); 73 extern void alpha_write_fp_reg_s (unsigned long reg, unsigned long val);
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