Searched refs:mask (Results 151 - 175 of 2076) sorted by relevance

1234567891011>>

/drivers/net/wireless/brcm80211/include/
H A Dbrcmu_utils.h181 * remark: the mask parameter should be a shifted mask.
183 static inline void brcmu_maskset32(u32 *var, u32 mask, u8 shift, u32 value) argument
185 value = (value << shift) & mask;
186 *var = (*var & ~mask) | value;
188 static inline u32 brcmu_maskget32(u32 var, u32 mask, u8 shift) argument
190 return (var & mask) >> shift;
192 static inline void brcmu_maskset16(u16 *var, u16 mask, u8 shift, u16 value) argument
194 value = (value << shift) & mask;
195 *var = (*var & ~mask) | valu
197 brcmu_maskget16(u16 var, u16 mask, u8 shift) argument
[all...]
/drivers/pinctrl/spear/
H A Dpinctrl-spear310.c29 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
61 .mask = PMX_FIRDA_MASK,
93 .mask = PMX_TIMER_0_1_MASK,
125 .mask = PMX_UART0_MODEM_MASK,
157 .mask = PMX_UART0_MODEM_MASK,
189 .mask = PMX_UART0_MODEM_MASK,
221 .mask = PMX_SSP_CS_MASK,
253 .mask = PMX_MII_MASK,
285 .mask = PMX_MII_MASK,
317 .mask
[all...]
/drivers/gpio/
H A Dgpio-tc3589x.c47 u8 mask = 1 << (offset % 8); local
54 return ret & mask;
108 int mask = 1 << (offset % 8); local
111 tc3589x_gpio->regs[REG_IBE][regoffset] |= mask;
115 tc3589x_gpio->regs[REG_IBE][regoffset] &= ~mask;
118 tc3589x_gpio->regs[REG_IS][regoffset] |= mask;
120 tc3589x_gpio->regs[REG_IS][regoffset] &= ~mask;
123 tc3589x_gpio->regs[REG_IEV][regoffset] |= mask;
125 tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask;
173 int mask local
184 int mask = 1 << (offset % 8); local
[all...]
/drivers/gpu/drm/i915/
H A Di915_cmd_parser.c126 .reg = { .offset = 1, .mask = 0x007FFFFC } ),
128 .reg = { .offset = 1, .mask = 0x007FFFFC },
131 .mask = MI_GLOBAL_GTT,
135 .reg = { .offset = 1, .mask = 0x007FFFFC },
138 .mask = MI_GLOBAL_GTT,
155 .mask = MI_GLOBAL_GTT,
162 .mask = MI_GLOBAL_GTT,
168 .mask = MI_REPORT_PERF_COUNT_GGTT,
174 .mask = MI_GLOBAL_GTT,
182 .mask
774 u32 mask; local
[all...]
/drivers/regulator/
H A Dlp3971.c31 static int lp3971_set_bits(struct lp3971 *lp3971, u8 reg, u16 mask, u16 val);
114 u16 mask = 1 << (1 + ldo); local
118 return (val & mask) != 0;
125 u16 mask = 1 << (1 + ldo); local
127 return lp3971_set_bits(lp3971, LP3971_LDO_ENABLE_REG, mask, mask);
134 u16 mask = 1 << (1 + ldo); local
136 return lp3971_set_bits(lp3971, LP3971_LDO_ENABLE_REG, mask, 0);
176 u16 mask = 1 << (buck * 2); local
180 return (val & mask) !
187 u16 mask = 1 << (buck * 2); local
196 u16 mask = 1 << (buck * 2); local
360 lp3971_set_bits(struct lp3971 *lp3971, u8 reg, u16 mask, u16 val) argument
[all...]
/drivers/rtc/
H A Drtc-sunxi.c62 #define SUNXI_GET(x, mask, shift) (((x) & ((mask) << (shift))) \
65 #define SUNXI_SET(x, mask, shift) (((x) & (mask)) << (shift))
72 #define SUNXI_DATE_GET_YEAR_VALUE(x, mask) SUNXI_GET(x, mask, 16)
93 #define SUNXI_DATE_SET_YEAR_VALUE(x, mask) SUNXI_SET(x, mask, 16)
132 unsigned int mask; /* mask fo member in struct:sunxi_rtc_data_year
325 sunxi_rtc_wait(struct sunxi_rtc_dev *chip, int offset, unsigned int mask, unsigned int ms_timeout) argument
[all...]
/drivers/staging/lustre/lustre/libcfs/linux/
H A Dlinux-cpu.c81 static void cfs_cpu_core_siblings(int cpu, cpumask_t *mask) argument
84 cpumask_copy(mask, topology_core_cpumask(cpu));
88 static void cfs_cpu_ht_siblings(int cpu, cpumask_t *mask) argument
90 cpumask_copy(mask, topology_thread_cpumask(cpu));
93 static void cfs_node_to_cpumask(int node, cpumask_t *mask) argument
95 cpumask_copy(mask, cpumask_of_node(node));
382 cfs_cpt_set_cpumask(struct cfs_cpt_table *cptab, int cpt, cpumask_t *mask) argument
386 if (cpus_weight(*mask) == 0 || any_online_cpu(*mask) == NR_CPUS) {
387 CDEBUG(D_INFO, "No online CPU is found in the CPU mask "
402 cfs_cpt_unset_cpumask(struct cfs_cpt_table *cptab, int cpt, cpumask_t *mask) argument
414 cpumask_t *mask; local
439 cpumask_t *mask; local
459 cfs_cpt_set_nodemask(struct cfs_cpt_table *cptab, int cpt, nodemask_t *mask) argument
473 cfs_cpt_unset_nodemask(struct cfs_cpt_table *cptab, int cpt, nodemask_t *mask) argument
505 nodemask_t *mask; local
729 cpumask_t *mask = NULL; local
[all...]
H A Dlinux-tracefile.c238 void cfs_print_to_console(struct ptldebug_header *hdr, int mask, argument
244 if ((mask & D_EMERG) != 0) {
247 } else if ((mask & D_ERROR) != 0) {
250 } else if ((mask & D_WARNING) != 0) {
253 } else if ((mask & (D_CONSOLE | libcfs_printk)) != 0) {
258 if ((mask & D_CONSOLE) != 0) {
/drivers/clk/qcom/
H A Dclk-rcg.c35 u32 mask; local
37 mask = SRC_SEL_MASK;
38 mask <<= s->src_sel_shift;
39 ns &= ~mask;
118 u32 mask; local
120 mask = BIT(p->pre_div_width) - 1;
121 mask <<= p->pre_div_shift;
122 ns &= ~mask;
130 u32 mask, mask_w; local
133 mask
161 u32 mask; local
180 u32 mask; local
429 u32 mask = 0; local
[all...]
H A Dclk-rcg2.c153 u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask; local
158 mask = BIT(rcg->mnd_width) - 1;
160 m &= mask;
163 n &= mask;
169 mask = BIT(rcg->hid_width) - 1;
171 hid_div &= mask;
218 u32 cfg, mask; local
222 mask = BIT(rcg->mnd_width) - 1;
224 rcg->cmd_rcgr + M_REG, mask, f->m);
229 rcg->cmd_rcgr + N_REG, mask, ~(
324 u32 mask = BIT(rcg->hid_width) - 1; local
370 u32 mask = BIT(rcg->hid_width) - 1; local
418 u32 mask = BIT(rcg->hid_width) - 1; local
438 u32 mask = BIT(rcg->hid_width) - 1; local
507 u32 mask = BIT(rcg->hid_width) - 1; local
[all...]
H A Dclk-branch.c58 u32 mask; local
60 mask = BRANCH_NOC_FSM_STATUS_MASK << BRANCH_NOC_FSM_STATUS_SHIFT;
61 mask |= BRANCH_CLK_OFF;
66 val &= mask;
/drivers/gpu/drm/tilcdc/
H A Dtilcdc_regs.h128 static inline void tilcdc_set(struct drm_device *dev, u32 reg, u32 mask) argument
130 tilcdc_write(dev, reg, tilcdc_read(dev, reg) | mask);
133 static inline void tilcdc_clear(struct drm_device *dev, u32 reg, u32 mask) argument
135 tilcdc_write(dev, reg, tilcdc_read(dev, reg) & ~mask);
150 static inline void tilcdc_clear_irqstatus(struct drm_device *dev, u32 mask) argument
152 tilcdc_write(dev, tilcdc_irqstatus_reg(dev), mask);
/drivers/media/pci/bt8xx/
H A Dbttv-gpio.c141 void bttv_gpio_inout(struct bttv_core *core, u32 mask, u32 outbits) argument
149 data = data & ~mask;
150 data = data | (mask & outbits);
171 void bttv_gpio_bits(struct bttv_core *core, u32 mask, u32 bits) argument
179 data = data & ~mask;
180 data = data | (mask & bits);
/drivers/mfd/
H A Dlp8788-irq.c91 u8 addr, mask, val; local
94 mask = _irq_to_mask(irq);
97 lp8788_update_bits(irqd->lp, addr, mask, val);
114 u8 status[NUM_REGS], addr, mask; local
123 mask = _irq_to_mask(i);
126 if (status[addr] & mask) {
H A Dpcf50633-gpio.c84 u8 reg, val, mask; local
90 mask = 1 << (gpio - PCF50633_GPIO1);
92 return pcf50633_reg_set_bit_mask(pcf, reg, mask, val);
/drivers/staging/comedi/drivers/
H A Daddi_apci_16xx.c64 unsigned int mask; local
68 mask = 0x000000ff;
70 mask = 0x0000ff00;
72 mask = 0x00ff0000;
74 mask = 0xff000000;
76 ret = comedi_dio_insn_config(dev, s, insn, data, mask);
/drivers/net/ethernet/freescale/
H A Dgianfar_ethtool.c922 /* Write a mask to filer cache */
923 static void gfar_set_mask(u32 mask, struct filer_table *tab) argument
926 tab->fe[tab->index].prop = mask;
931 static void gfar_set_parse_bits(u32 value, u32 mask, struct filer_table *tab) argument
933 gfar_set_mask(mask, tab);
940 static void gfar_set_general_attribute(u32 value, u32 mask, u32 flag, argument
943 gfar_set_mask(mask, tab);
949 /* For setting a tuple of value and mask of type flag
952 * value: 0x0A000000 mask: FF000000 flag: RQFPR_IPV4
954 * Ethtool gives us a value=0 and mask
963 gfar_set_attribute(u32 value, u32 mask, u32 flag, struct filer_table *tab) argument
1021 gfar_set_basic_ip(struct ethtool_tcpip4_spec *value, struct ethtool_tcpip4_spec *mask, struct filer_table *tab) argument
1041 gfar_set_user_ip(struct ethtool_usrip4_spec *value, struct ethtool_usrip4_spec *mask, struct filer_table *tab) argument
1060 gfar_set_ether(struct ethhdr *value, struct ethhdr *mask, struct filer_table *tab) argument
1398 gfar_swap_bits(struct gfar_filer_entry *a1, struct gfar_filer_entry *a2, struct gfar_filer_entry *b1, struct gfar_filer_entry *b2, u32 mask) argument
[all...]
/drivers/gpu/drm/nouveau/core/engine/perfmon/
H A Ddaemon.c31 u32 mask = 0x00000000; local
36 mask |= 1 << (ctr->signal[i] - dom->signal);
38 nv_wr32(ppm, 0x10a504 + (ctr->slot * 0x10), mask);
/drivers/media/rc/img-ir/
H A Dimg-ir-sanyo.c60 data_m = in->mask & 0xff;
67 addr_m = (in->mask >> 8) & 0x1fff;
74 out->mask = (u64)data_m << 34 |
/drivers/power/reset/
H A Dsyscon-reboot.c30 u32 mask; member in struct:syscon_reboot_context
42 regmap_write(ctx->map, ctx->offset, ctx->mask);
67 if (of_property_read_u32(pdev->dev.of_node, "mask", &ctx->mask))
/drivers/scsi/fnic/
H A Dvnic_intr.h54 u32 mask; /* 0x20 */ member in struct:vnic_intr_ctrl
70 iowrite32(0, &intr->ctrl->mask);
75 iowrite32(1, &intr->ctrl->mask);
/drivers/video/fbdev/
H A Datafb_iplan2p2.c107 u32 pval[4], v, v1, mask; local
113 mask = 0xff00ff00;
128 pval[0] = (*src32++ << 8) & mask;
130 pval[0] = dst32[0] & mask;
135 v1 = v & mask;
141 dst32[0] = (dst32[0] & mask) | pval[0];
149 u32 pval[4], v, v1, mask; local
155 mask = 0xff00ff;
170 pval[0] = dst32[-1] & mask;
172 pval[0] = (*--src32 >> 8) & mask;
[all...]
/drivers/clocksource/
H A Dexynos_mct.c94 u32 mask; local
103 mask = 1 << 3; /* L_TCON write status */
106 mask = 1 << 1; /* L_ICNTB write status */
109 mask = 1 << 0; /* L_TCNTB write status */
118 mask = 1 << 16; /* G_TCON write status */
122 mask = 1 << 0; /* G_COMP0_L write status */
126 mask = 1 << 1; /* G_COMP0_U write status */
130 mask = 1 << 2; /* G_COMP0_ADD_INCR w status */
134 mask = 1 << 0; /* G_CNT_L write status */
138 mask
352 unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START; local
[all...]
/drivers/iommu/
H A Dirq_remapping.h65 int (*set_affinity)(struct irq_data *data, const struct cpumask *mask,
/drivers/media/common/
H A Dbtcx-risc.h24 unsigned int n, int mask);

Completed in 629 milliseconds

1234567891011>>