Searched refs:parent_name (Results 26 - 50 of 92) sorted by relevance

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/drivers/clk/
H A Dclk-gpio-gate.c67 * @parent_name: name of this clock's parent
71 const char *parent_name, struct gpio_desc *gpiod,
111 init.parent_names = (parent_name ? &parent_name : NULL);
112 init.num_parents = (parent_name ? 1 : 0);
151 const char *parent_name; local
172 parent_name = of_clk_get_parent_name(data->node, 0);
174 clk = clk_register_gpio_gate(NULL, clk_name, parent_name, gpiod, 0);
70 clk_register_gpio_gate(struct device *dev, const char *name, const char *parent_name, struct gpio_desc *gpiod, unsigned long flags) argument
H A Dclk-nomadik.c259 const char *parent_name, u32 id)
278 init.parent_names = (parent_name ? &parent_name : NULL);
279 init.num_parents = (parent_name ? 1 : 0);
351 const char *parent_name, u8 id)
370 init.parent_names = (parent_name ? &parent_name : NULL);
371 init.num_parents = (parent_name ? 1 : 0);
515 const char *parent_name; local
526 parent_name
258 pll_clk_register(struct device *dev, const char *name, const char *parent_name, u32 id) argument
350 src_clk_register(struct device *dev, const char *name, const char *parent_name, u8 id) argument
538 const char *parent_name; local
562 const char *parent_name; local
[all...]
H A Dclk-gate.c114 * @parent_name: name of this clock's parent
122 const char *parent_name, unsigned long flags,
147 init.parent_names = (parent_name ? &parent_name: NULL);
148 init.num_parents = (parent_name ? 1 : 0);
121 clk_register_gate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock) argument
H A Dclk-ls1x.c52 const char *name, const char *parent_name, unsigned long flags)
68 init.parent_names = (parent_name ? &parent_name : NULL);
69 init.num_parents = (parent_name ? 1 : 0);
51 clk_register_pll(struct device *dev, const char *name, const char *parent_name, unsigned long flags) argument
H A Dclk-fractional-divider.c100 const char *name, const char *parent_name, unsigned long flags,
117 init.parent_names = parent_name ? &parent_name : NULL;
118 init.num_parents = parent_name ? 1 : 0;
99 clk_register_fractional_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, u8 clk_divider_flags, spinlock_t *lock) argument
/drivers/clk/at91/
H A Dclk-system.c104 const char *parent_name, u8 id, int irq)
111 if (!parent_name || id > SYSTEM_MAX_ID)
120 init.parent_names = &parent_name;
153 const char *parent_name; local
169 parent_name = of_clk_get_parent_name(sysclknp, 0);
171 clk = at91_clk_register_system(pmc, name, parent_name, id, irq);
103 at91_clk_register_system(struct at91_pmc *pmc, const char *name, const char *parent_name, u8 id, int irq) argument
H A Dclk-usb.c196 const char *parent_name)
208 init.parent_names = &parent_name;
311 const char *parent_name, const u32 *divisors)
323 init.parent_names = &parent_name;
370 const char *parent_name; local
373 parent_name = of_clk_get_parent_name(np, 0);
374 if (!parent_name)
379 clk = at91sam9n12_clk_register_usb(pmc, name, parent_name);
390 const char *parent_name; local
394 parent_name
195 at91sam9n12_clk_register_usb(struct at91_pmc *pmc, const char *name, const char *parent_name) argument
310 at91rm9200_clk_register_usb(struct at91_pmc *pmc, const char *name, const char *parent_name, const u32 *divisors) argument
[all...]
/drivers/clk/versatile/
H A Dclk-versatile.c65 const char *parent_name; local
83 parent_name = of_clk_get_parent_name(np, 0);
84 clk = icst_clk_register(NULL, desc, clk_name, parent_name, cm_base);
/drivers/clk/hisilicon/
H A Dclkgate-separated.c100 const char *parent_name,
118 init.parent_names = (parent_name ? &parent_name : NULL);
119 init.num_parents = (parent_name ? 1 : 0);
99 hisi_register_clkgate_sep(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock) argument
/drivers/clk/mxs/
H A Dclk-div.c77 struct clk *mxs_clk_div(const char *name, const char *parent_name, argument
91 init.parent_names = (parent_name ? &parent_name: NULL);
92 init.num_parents = (parent_name ? 1 : 0);
H A Dclk-frac.c111 struct clk *mxs_clk_frac(const char *name, const char *parent_name, argument
125 init.parent_names = (parent_name ? &parent_name: NULL);
126 init.num_parents = (parent_name ? 1 : 0);
H A Dclk-ref.c128 struct clk *mxs_clk_ref(const char *name, const char *parent_name, argument
142 init.parent_names = (parent_name ? &parent_name: NULL);
143 init.num_parents = (parent_name ? 1 : 0);
/drivers/clk/spear/
H A Dclk.h114 const char *parent_name, unsigned long flags, void __iomem *reg,
117 struct clk *clk_register_frac(const char *name, const char *parent_name,
120 struct clk *clk_register_gpt(const char *name, const char *parent_name, unsigned
124 const char *vco_gate_name, const char *parent_name,
/drivers/clk/tegra/
H A Dclk-pll-out.c91 const char *parent_name, void __iomem *reg, u8 enb_bit_idx,
105 init.parent_names = (parent_name ? &parent_name : NULL);
106 init.num_parents = (parent_name ? 1 : 0);
90 tegra_clk_register_pll_out(const char *name, const char *parent_name, void __iomem *reg, u8 enb_bit_idx, u8 rst_bit_idx, unsigned long flags, u8 pll_out_flags, spinlock_t *lock) argument
H A Dclk.h86 const char *parent_name, void __iomem *reg,
261 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
266 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
271 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
277 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
283 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
289 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
296 const char *parent_name,
301 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
329 const char *parent_name, voi
472 const char *parent_name; member in union:tegra_periph_init_data::__anon466
[all...]
/drivers/clk/ti/
H A Dinterface.c40 const char *parent_name; local
62 parent_name = of_clk_get_parent_name(node, 0);
63 if (!parent_name) {
69 init.parent_names = &parent_name;
/drivers/clk/keystone/
H A Dgate.c162 * @parent_name: name of clock's parent
168 const char *parent_name,
183 init.parent_names = (parent_name ? &parent_name : NULL);
184 init.num_parents = (parent_name ? 1 : 0);
205 const char *parent_name; local
237 parent_name = of_clk_get_parent_name(node, 0);
238 if (!parent_name) {
243 clk = clk_register_psc(NULL, clk_name, parent_name, data, lock);
166 clk_register_psc(struct device *dev, const char *name, const char *parent_name, struct clk_psc_data *psc_data, spinlock_t *lock) argument
/drivers/clk/ux500/
H A Dclk-sysctrl.c181 const char *parent_name,
188 const char **parent_names = (parent_name ? &parent_name : NULL);
189 u8 num_parents = (parent_name ? 1 : 0);
198 const char *parent_name,
206 const char **parent_names = (parent_name ? &parent_name : NULL);
207 u8 num_parents = (parent_name ? 1 : 0);
179 clk_reg_sysctrl_gate(struct device *dev, const char *name, const char *parent_name, u16 reg_sel, u8 reg_mask, u8 reg_bits, unsigned long enable_delay_us, unsigned long flags) argument
196 clk_reg_sysctrl_gate_fixed_rate(struct device *dev, const char *name, const char *parent_name, u16 reg_sel, u8 reg_mask, u8 reg_bits, unsigned long rate, unsigned long enable_delay_us, unsigned long flags) argument
/drivers/clk/samsung/
H A Dclk.h61 * @parent_name: optional parent clock name.
68 const char *parent_name; member in struct:samsung_fixed_rate_clock
77 .parent_name = pname, \
86 * @parent_name: parent clock name.
94 const char *parent_name; member in struct:samsung_fixed_factor_clock
104 .parent_name = pname, \
170 * @parent_name: name of the parent clock.
181 const char *parent_name; member in struct:samsung_div_clock
196 .parent_name = pname, \
223 * @parent_name
234 const char *parent_name; member in struct:samsung_gate_clock
295 const char *parent_name; member in struct:samsung_pll_clock
[all...]
/drivers/clk/st/
H A Dclkgen-pll.c393 static struct clk * __init clkgen_pll_register(const char *parent_name, argument
410 init.parent_names = &parent_name;
431 static struct clk * __init clkgen_c65_lsdiv_register(const char *parent_name, argument
436 clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0, 1, 2);
470 const char *parent_name; local
474 parent_name = of_clk_get_parent_name(np, 0);
475 if (!parent_name)
500 clk_data->clks[0] = clkgen_pll_register(parent_name,
529 clk_data->clks[2] = clkgen_pll_register(parent_name,
546 static struct clk * __init clkgen_odf_register(const char *parent_name, argument
644 const char *parent_name, *pll_name; local
727 const char *parent_name; local
[all...]
/drivers/clk/shmobile/
H A Dclk-r8a7779.c98 const char *parent_name = "plla"; local
103 parent_name = of_clk_get_parent_name(np, 0);
120 return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
H A Dclk-div6.c120 const char *parent_name; local
153 parent_name = of_clk_get_parent_name(np, 0);
154 if (parent_name == NULL) {
164 init.parent_names = &parent_name;
/drivers/clk/socfpga/
H A Dclk-periph.c59 const char *parent_name; local
93 parent_name = of_clk_get_parent_name(node, 0);
94 init.parent_names = &parent_name;
H A Dclk-pll.c91 const char *parent_name[SOCFPGA_MAX_PARENTS]; local
114 while (i < SOCFPGA_MAX_PARENTS && (parent_name[i] =
119 init.parent_names = parent_name;
/drivers/clk/mmp/
H A Dclk-apbc.c123 struct clk *mmp_clk_register_apbc(const char *name, const char *parent_name, argument
138 init.parent_names = (parent_name ? &parent_name : NULL);
139 init.num_parents = (parent_name ? 1 : 0);

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