Searched refs:readl_relaxed (Results 101 - 125 of 161) sorted by relevance

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/drivers/clk/spear/
H A Dclk-gpt-synth.c65 val = readl_relaxed(gpt->reg);
/drivers/clocksource/
H A Dpxa_timer.c52 #define timer_readl(reg) readl_relaxed(timer_base + (reg))
H A Dtimer-keystone.c54 return readl_relaxed(timer.base + rg);
H A Dmxs_timer.c227 return ~readl_relaxed(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1));
H A Dnomadik-mtu.c89 return ~readl_relaxed(mtu_base + MTU_VAL(0));
/drivers/gpu/drm/armada/
H A Darmada_debugfs.c44 uint32_t v = readl_relaxed(dcrtc->base + i);
H A Darmada_crtc.c98 val &= readl_relaxed(reg);
385 val = readl_relaxed(base + LCD_SPU_ADV_REG);
420 u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR);
452 if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask)
706 readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN);
781 para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1);
/drivers/irqchip/
H A Dirq-dw-apb-ictl.c40 stat = readl_relaxed(gc->reg_base +
H A Dirq-vic.c220 while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
237 while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
/drivers/pinctrl/vt8500/
H A Dpinctrl-wmt.c40 val = readl_relaxed(data->base + reg);
50 val = readl_relaxed(data->base + reg);
507 val = readl_relaxed(data->base + reg_dir);
526 return !!(readl_relaxed(data->base + reg_data_in) & BIT(bit));
/drivers/soc/tegra/fuse/
H A Dfuse-tegra20.c176 return readl_relaxed(fuse_base + FUSE_BEGIN + offset);
H A Dfuse-tegra30.c73 val = readl_relaxed(fuse_base + FUSE_BEGIN + offset);
/drivers/phy/
H A Dphy-qcom-apq8064-sata.c88 if (readl_relaxed(addr) & mask)
94 return (readl_relaxed(addr) & mask) ? 0 : -ETIMEDOUT;
/drivers/pwm/
H A Dpwm-atmel.c75 return readl_relaxed(chip->base + offset);
89 return readl_relaxed(chip->base + base + offset);
/drivers/bus/
H A Darm-cci.c200 rev = readl_relaxed(cci_ctrl_base + CCI_PID2) & CCI_PID2_REV_MASK;
263 return readl_relaxed(pmu->base + CCI_PMU_CNTR_BASE(idx) + offset);
289 u32 n_cnts = (readl_relaxed(cci_ctrl_base + CCI_PMCR) &
480 val = readl_relaxed(cci_ctrl_base + CCI_PMCR) | CCI_PMCR_CEN;
495 val = readl_relaxed(cci_ctrl_base + CCI_PMCR) & ~CCI_PMCR_CEN;
762 while (readl_relaxed(cci_ctrl_base + CCI_CTRL_STATUS) & 0x1)
/drivers/net/irda/
H A Dpxaficp_ir.c295 si->last_oscr = readl_relaxed(OSCR);
306 si->last_oscr = readl_relaxed(OSCR);
322 si->last_oscr = readl_relaxed(OSCR);
376 si->last_oscr = readl_relaxed(OSCR);
476 si->last_oscr = readl_relaxed(OSCR);
552 while ((unsigned)(readl_relaxed(OSCR) - si->last_oscr)/4 < mtt)
/drivers/spmi/
H A Dspmi-pmic-arb.c136 return readl_relaxed(dev->base + offset);
379 status = readl_relaxed(pa->intr + SPMI_PIC_IRQ_STATUS(apid));
404 status = readl_relaxed(intr +
442 status = readl_relaxed(pa->intr + SPMI_PIC_ACC_ENABLE(apid));
463 status = readl_relaxed(pa->intr + SPMI_PIC_ACC_ENABLE(apid));
703 pa->mapping_table[i] = readl_relaxed(
/drivers/gpio/
H A Dgpio-davinci.c92 temp = readl_relaxed(&g->dir);
128 return (1 << offset) & readl_relaxed(&g->in_data);
355 status = readl_relaxed(&g->intstat) & mask;
/drivers/i2c/busses/
H A Di2c-hix5hd2.c104 u32 val = readl_relaxed(priv->regs + HIX5I2C_SR);
133 val = readl_relaxed(priv->regs + HIX5I2C_CTRL);
238 data = readl_relaxed(priv->regs + HIX5I2C_RXR);
/drivers/clk/tegra/
H A Dclk-tegra124.c1038 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
1058 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1076 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1082 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1091 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1099 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
H A Dclk-pll.c186 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
189 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
258 val = readl_relaxed(lock_addr);
278 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
302 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
320 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
1583 val = readl_relaxed(clk_base + pll_params->base_reg);
1584 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
/drivers/pinctrl/
H A Dpinctrl-rockchip.c880 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1395 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1398 polarity = readl_relaxed(bank->reg_base +
1400 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
1435 data = readl_relaxed(bank->reg_base + GPIO_INTEN);
1459 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1470 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1471 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
/drivers/clk/mxs/
H A Dclk-imx23.c62 val = readl_relaxed(SAIF);
/drivers/clk/rockchip/
H A Dclk-cpu.c93 u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg);
/drivers/iio/adc/
H A Drockchip_saradc.c105 info->last_val = readl_relaxed(info->regs + SARADC_DATA);

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