1/*
2 * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
15 *
16 */
17
18#include <linux/device.h>
19#include <linux/clk.h>
20#include <linux/err.h>
21#include <linux/io.h>
22#include <linux/kernel.h>
23#include <linux/of_device.h>
24#include <linux/of_address.h>
25#include <linux/platform_device.h>
26#include <linux/random.h>
27
28#include <soc/tegra/fuse.h>
29
30#include "fuse.h"
31
32#define FUSE_BEGIN	0x100
33
34/* Tegra30 and later */
35#define FUSE_VENDOR_CODE	0x100
36#define FUSE_FAB_CODE		0x104
37#define FUSE_LOT_CODE_0		0x108
38#define FUSE_LOT_CODE_1		0x10c
39#define FUSE_WAFER_ID		0x110
40#define FUSE_X_COORDINATE	0x114
41#define FUSE_Y_COORDINATE	0x118
42
43#define FUSE_HAS_REVISION_INFO	BIT(0)
44
45enum speedo_idx {
46	SPEEDO_TEGRA30 = 0,
47	SPEEDO_TEGRA114,
48	SPEEDO_TEGRA124,
49};
50
51struct tegra_fuse_info {
52	int		size;
53	int		spare_bit;
54	enum speedo_idx	speedo_idx;
55};
56
57static void __iomem *fuse_base;
58static struct clk *fuse_clk;
59static struct tegra_fuse_info *fuse_info;
60
61u32 tegra30_fuse_readl(const unsigned int offset)
62{
63	u32 val;
64
65	/*
66	 * early in the boot, the fuse clock will be enabled by
67	 * tegra_init_fuse()
68	 */
69
70	if (fuse_clk)
71		clk_prepare_enable(fuse_clk);
72
73	val = readl_relaxed(fuse_base + FUSE_BEGIN + offset);
74
75	if (fuse_clk)
76		clk_disable_unprepare(fuse_clk);
77
78	return val;
79}
80
81static struct tegra_fuse_info tegra30_info = {
82	.size			= 0x2a4,
83	.spare_bit		= 0x144,
84	.speedo_idx		= SPEEDO_TEGRA30,
85};
86
87static struct tegra_fuse_info tegra114_info = {
88	.size			= 0x2a0,
89	.speedo_idx		= SPEEDO_TEGRA114,
90};
91
92static struct tegra_fuse_info tegra124_info = {
93	.size			= 0x300,
94	.speedo_idx		= SPEEDO_TEGRA124,
95};
96
97static const struct of_device_id tegra30_fuse_of_match[] = {
98	{ .compatible = "nvidia,tegra30-efuse", .data = &tegra30_info },
99	{ .compatible = "nvidia,tegra114-efuse", .data = &tegra114_info },
100	{ .compatible = "nvidia,tegra124-efuse", .data = &tegra124_info },
101	{},
102};
103
104static int tegra30_fuse_probe(struct platform_device *pdev)
105{
106	const struct of_device_id *of_dev_id;
107
108	of_dev_id = of_match_device(tegra30_fuse_of_match, &pdev->dev);
109	if (!of_dev_id)
110		return -ENODEV;
111
112	fuse_clk = devm_clk_get(&pdev->dev, NULL);
113	if (IS_ERR(fuse_clk)) {
114		dev_err(&pdev->dev, "missing clock");
115		return PTR_ERR(fuse_clk);
116	}
117
118	platform_set_drvdata(pdev, NULL);
119
120	if (tegra_fuse_create_sysfs(&pdev->dev, fuse_info->size,
121				    tegra30_fuse_readl))
122		return -ENODEV;
123
124	dev_dbg(&pdev->dev, "loaded\n");
125
126	return 0;
127}
128
129static struct platform_driver tegra30_fuse_driver = {
130	.probe = tegra30_fuse_probe,
131	.driver = {
132		.name = "tegra_fuse",
133		.owner = THIS_MODULE,
134		.of_match_table = tegra30_fuse_of_match,
135	}
136};
137
138static int __init tegra30_fuse_init(void)
139{
140	return platform_driver_register(&tegra30_fuse_driver);
141}
142postcore_initcall(tegra30_fuse_init);
143
144/* Early boot code. This code is called before the devices are created */
145
146typedef void (*speedo_f)(struct tegra_sku_info *sku_info);
147
148static speedo_f __initdata speedo_tbl[] = {
149	[SPEEDO_TEGRA30]	= tegra30_init_speedo_data,
150	[SPEEDO_TEGRA114]	= tegra114_init_speedo_data,
151	[SPEEDO_TEGRA124]	= tegra124_init_speedo_data,
152};
153
154static void __init tegra30_fuse_add_randomness(void)
155{
156	u32 randomness[12];
157
158	randomness[0] = tegra_sku_info.sku_id;
159	randomness[1] = tegra_read_straps();
160	randomness[2] = tegra_read_chipid();
161	randomness[3] = tegra_sku_info.cpu_process_id << 16;
162	randomness[3] |= tegra_sku_info.core_process_id;
163	randomness[4] = tegra_sku_info.cpu_speedo_id << 16;
164	randomness[4] |= tegra_sku_info.soc_speedo_id;
165	randomness[5] = tegra30_fuse_readl(FUSE_VENDOR_CODE);
166	randomness[6] = tegra30_fuse_readl(FUSE_FAB_CODE);
167	randomness[7] = tegra30_fuse_readl(FUSE_LOT_CODE_0);
168	randomness[8] = tegra30_fuse_readl(FUSE_LOT_CODE_1);
169	randomness[9] = tegra30_fuse_readl(FUSE_WAFER_ID);
170	randomness[10] = tegra30_fuse_readl(FUSE_X_COORDINATE);
171	randomness[11] = tegra30_fuse_readl(FUSE_Y_COORDINATE);
172
173	add_device_randomness(randomness, sizeof(randomness));
174}
175
176static void __init legacy_fuse_init(void)
177{
178	switch (tegra_get_chip_id()) {
179	case TEGRA30:
180		fuse_info = &tegra30_info;
181		break;
182	case TEGRA114:
183		fuse_info = &tegra114_info;
184		break;
185	case TEGRA124:
186		fuse_info = &tegra124_info;
187		break;
188	default:
189		return;
190	}
191
192	fuse_base = ioremap(TEGRA_FUSE_BASE, TEGRA_FUSE_SIZE);
193}
194
195bool __init tegra30_spare_fuse(int spare_bit)
196{
197	u32 offset = fuse_info->spare_bit + spare_bit * 4;
198
199	return tegra30_fuse_readl(offset) & 1;
200}
201
202void __init tegra30_init_fuse_early(void)
203{
204	struct device_node *np;
205	const struct of_device_id *of_match;
206
207	np = of_find_matching_node_and_match(NULL, tegra30_fuse_of_match,
208						&of_match);
209	if (np) {
210		fuse_base = of_iomap(np, 0);
211		fuse_info = (struct tegra_fuse_info *)of_match->data;
212	} else
213		legacy_fuse_init();
214
215	if (!fuse_base) {
216		pr_warn("fuse DT node missing and unknown chip id: 0x%02x\n",
217			tegra_get_chip_id());
218		return;
219	}
220
221	tegra_init_revision();
222	speedo_tbl[fuse_info->speedo_idx](&tegra_sku_info);
223	tegra30_fuse_add_randomness();
224}
225