Searched refs:reg_base (Results 101 - 125 of 155) sorted by relevance

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/drivers/net/can/
H A Dxilinx_can.c127 * @reg_base: Ioremapped address to registers
142 void __iomem *reg_base; member in struct:xcan_priv
172 iowrite32(val, priv->reg_base + reg);
185 return ioread32(priv->reg_base + reg);
199 iowrite32be(val, priv->reg_base + reg);
212 return ioread32be(priv->reg_base + reg);
1080 priv->reg_base = addr;
1149 netdev_dbg(ndev, "reg_base=0x%p irq=%d clock=%d, tx fifo depth:%d\n",
1150 priv->reg_base, ndev->irq, priv->can.clock.freq,
H A Dat91_can.c144 void __iomem *reg_base; member in struct:at91_priv
295 return __raw_readl(priv->reg_base + reg);
301 __raw_writel(value, priv->reg_base + reg);
1354 priv->reg_base = addr;
1376 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1377 priv->reg_base, dev->irq);
1401 iounmap(priv->reg_base);
/drivers/video/fbdev/exynos/
H A Dexynos_mipi_dsi.c389 dsim->reg_base = devm_ioremap_resource(&pdev->dev, res);
390 if (IS_ERR(dsim->reg_base)) {
391 ret = PTR_ERR(dsim->reg_base);
/drivers/macintosh/
H A Dwindfarm_fcu_controls.c171 int rc, reg_base, shift = pv->rpm_shift; local
189 reg_base = 0x11;
191 reg_base = 0x10;
193 rc = wf_fcu_read_reg(pv, reg_base + (fan->id * 2), buf, 2);
/drivers/media/pci/solo6x10/
H A Dsolo6x10-core.c154 if (solo_dev->reg_base) {
167 pci_iounmap(pdev, solo_dev->reg_base);
508 solo_dev->reg_base = pci_ioremap_bar(pdev, 0);
509 if (solo_dev->reg_base == NULL) {
/drivers/net/can/cc770/
H A Dcc770.h188 void __iomem *reg_base; /* ioremap'ed address to registers */ member in struct:cc770_priv
/drivers/ntb/
H A Dntb_hw.h119 void __iomem *reg_base; member in struct:ntb_device
/drivers/pcmcia/
H A Dm32r_cfc.c318 unsigned int reg_base; local
320 reg_base = (unsigned int)PLD_CFRSTCR;
321 reg_base |= pcc_sockets << 8;
322 request_region(reg_base, 0x20, "m32r_cfc");
/drivers/irqchip/
H A Dirq-s3c24xx.c1251 void __iomem *reg_base; local
1254 reg_base = of_iomap(np, 0);
1255 if (!reg_base) {
1285 intc->reg_pending = reg_base + ctrl->offset;
1286 intc->reg_mask = reg_base + ctrl->offset + 0x4;
1298 intc->reg_pending = reg_base + ctrl->offset;
1299 intc->reg_mask = reg_base + ctrl->offset + 0x08;
1300 intc->reg_intpnd = reg_base + ctrl->offset + 0x10;
H A Dirq-imgpdc.c406 gc->reg_base = priv->pdc_base;
420 gc->reg_base = priv->pdc_base;
H A Dirq-bcm7120-l2.c184 gc->reg_base = data->base;
H A Dirq-brcmstb-l2.c164 gc->reg_base = data->base;
/drivers/clk/rockchip/
H A Dclk-rk3188.c709 void __iomem *reg_base; local
712 reg_base = of_iomap(np, 0);
713 if (!reg_base) {
718 rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
736 rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
H A Dclk-rk3288.c767 void __iomem *reg_base; local
770 reg_base = of_iomap(np, 0);
771 if (!reg_base) {
776 rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
809 rockchip_register_softrst(np, 12, reg_base + RK3288_SOFTRST_CON(0),
H A Dclk.h153 int nrates, void __iomem *reg_base, spinlock_t *lock);
/drivers/gpio/
H A Dgpio-dwapb.c95 void __iomem *reg_base = gpio->regs; local
97 return bgc->read_reg(reg_base + offset);
104 void __iomem *reg_base = gpio->regs; local
106 bgc->write_reg(reg_base + offset, val);
328 irq_gc->reg_base = gpio->regs;
/drivers/iio/adc/
H A Dat91_adc.c140 (readl_relaxed(st->reg_base + reg))
142 (writel_relaxed(val, st->reg_base + reg))
202 void __iomem *reg_base; member in struct:at91_adc_state
1168 st->reg_base = devm_ioremap_resource(&pdev->dev, res);
1169 if (IS_ERR(st->reg_base)) {
1170 return PTR_ERR(st->reg_base);
H A Dtwl4030-madc.c269 * @reg_base - Base address of the first channel
277 u8 reg_base, unsigned
286 reg = reg_base + (2 * i);
276 twl4030_madc_read_channels(struct twl4030_madc_data *madc, u8 reg_base, unsigned long channels, int *buf, bool raw) argument
/drivers/video/fbdev/
H A Dmx3fb.c242 void __iomem *reg_base; member in struct:mx3fb_data
349 return __raw_readl(mx3fb->reg_base + reg);
354 __raw_writel(value, mx3fb->reg_base + reg);
1581 mx3fb->reg_base = ioremap(sdc_reg->start, resource_size(sdc_reg));
1582 if (!mx3fb->reg_base) {
1587 pr_debug("Remapped %pR at %p\n", sdc_reg, mx3fb->reg_base);
1621 iounmap(mx3fb->reg_base);
1642 iounmap(mx3fb->reg_base);
/drivers/gpu/drm/exynos/
H A Dexynos_dp_core.h155 void __iomem *reg_base; member in struct:exynos_dp_device
/drivers/net/can/mscan/
H A Dmscan.h285 void __iomem *reg_base; /* ioremap'ed address to registers */ member in struct:mscan_priv
/drivers/pinctrl/
H A Dpinctrl-bcm281xx.c86 * @reg_base - base of pinctrl registers
89 void __iomem *reg_base; member in struct:bcm281xx_pinctrl_data
1412 pdata->reg_base = devm_ioremap_resource(&pdev->dev, res);
1413 if (IS_ERR(pdata->reg_base)) {
1419 pdata->regmap = devm_regmap_init_mmio(&pdev->dev, pdata->reg_base,
/drivers/pinctrl/samsung/
H A Dpinctrl-samsung.c427 void __iomem *reg_base; local
434 pin_to_reg_bank(drvdata, pin - drvdata->ctrl->base, &reg_base,
448 data = readl(reg_base + cfg_reg);
454 writel(data, reg_base + cfg_reg);
/drivers/clk/samsung/
H A Dclk-pll.c882 const void __iomem *reg_base; member in struct:samsung_clk_pll2550x
895 pll_stat = __raw_readl(pll->reg_base + pll->offset * 3);
914 const char *pname, const void __iomem *reg_base,
934 pll->reg_base = reg_base;
913 samsung_clk_register_pll2550x(const char *name, const char *pname, const void __iomem *reg_base, const unsigned long offset) argument
/drivers/input/mouse/
H A Dalps.c1623 int reg_base, bool enable)
1630 reg_val = alps_command_mode_read_reg(psmouse, reg_base + 0x0008);
1663 static int alps_probe_trackstick_v3(struct psmouse *psmouse, int reg_base) argument
1670 reg_val = alps_command_mode_read_reg(psmouse, reg_base + 0x08);
1682 static int alps_setup_trackstick_v3(struct psmouse *psmouse, int reg_base) argument
1688 if (alps_passthrough_mode_v3(psmouse, reg_base, true))
1730 reg_base + 0x08, 0x82) ||
1736 if (alps_passthrough_mode_v3(psmouse, reg_base, false))
1622 alps_passthrough_mode_v3(struct psmouse *psmouse, int reg_base, bool enable) argument

Completed in 513 milliseconds

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