Searched refs:regno (Results 76 - 100 of 157) sorted by relevance

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/drivers/video/fbdev/
H A Dxilinxfb.c198 xilinx_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, argument
203 if (regno >= PALETTE_ENTRIES_NO)
219 palette[regno] = (red << RED_SHIFT) | (green << GREEN_SHIFT) |
H A Dau1100fb.c235 int au1100fb_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, unsigned transp, struct fb_info *fbi) argument
244 if (regno > (AU1100_LCD_NBR_PALETTE_ENTRIES - 1))
255 if (regno > 16)
286 palette[regno] = value;
H A Dbf537-lq035.c587 static int bfin_lq035_fb_setcolreg(u_int regno, u_int red, u_int green, argument
591 if (regno >= NBR_PALETTE)
602 if (regno > 16)
614 ((u32 *) (info->pseudo_palette))[regno] = value;
H A Dbf54x-lq043fb.c381 static int bfin_bf54x_fb_setcolreg(u_int regno, u_int red, u_int green, argument
385 if (regno >= BFIN_LCD_NBR_PALETTE_ENTRIES)
397 if (regno > 16)
409 ((u32 *) (info->pseudo_palette))[regno] = value;
H A Dbfin-t350mcqb-fb.c303 static int bfin_t350mcqb_fb_setcolreg(u_int regno, u_int red, u_int green, argument
307 if (regno >= BFIN_LCD_NBR_PALETTE_ENTRIES)
319 if (regno > 16)
331 ((u32 *) (info->pseudo_palette))[regno] = value;
H A Dchipsfb.c79 static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
151 static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, argument
154 if (regno > 255)
159 outb(regno, 0x3c8);
H A Ds3fb.c926 static int s3fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, argument
932 if (regno >= 16)
938 outb(regno*16, VGA_PEL_IW);
941 outb(regno, VGA_PEL_IW);
948 if (regno >= 256)
952 outb(regno, VGA_PEL_IW);
958 if (regno >= 16)
962 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) |
965 ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) |
971 if (regno >
[all...]
H A Datmel_lcdfb.c784 * @regno: Which register in the CLUT we are programming
807 static int atmel_lcdfb_setcolreg(unsigned int regno, unsigned int red, argument
823 if (regno < 16) {
830 pal[regno] = val;
836 if (regno < 256) {
860 lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val);
866 if (regno < 2) {
867 val = (regno == 0) ? 0x00 : 0x1F;
868 lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val);
H A Dstifb.c918 stifb_setcolreg(u_int regno, u_int red, u_int green, argument
924 if (regno >= NR_PALETTE)
948 if (regno < 16)
949 ((u32 *)fb->info.pseudo_palette)[regno] =
950 regno << var->red.offset |
951 regno << var->green.offset |
952 regno << var->blue.offset;
955 WRITE_IMAGE_COLOR(fb, regno, color);
H A Dtgafb.c507 * @regno: boolean, 0 copy local, 1 get_user() function
515 tgafb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, argument
522 if (regno > 255)
529 BT485_WRITE(par, regno, BT485_ADDR_PAL_WRITE);
535 BT459_LOAD_ADDR(par, regno);
541 if (regno < 16) {
542 u32 value = (regno << 16) | (regno << 8) | regno;
543 ((u32 *)info->pseudo_palette)[regno]
[all...]
H A Dpxa168fb.c492 pxa168fb_setcolreg(unsigned int regno, unsigned int red, unsigned int green, argument
502 if (info->fix.visual == FB_VISUAL_TRUECOLOR && regno < 16) {
506 fbi->pseudo_palette[regno] = val;
509 if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR && regno < 256) {
512 writel(0x8300 | regno, fbi->reg_base + LCD_SPU_SRAM_CTRL);
H A Dcg14.c235 * @regno: boolean, 0 copy local, 1 get_user() function
242 static int cg14_setcolreg(unsigned regno, argument
251 if (regno >= 256)
260 sbus_writel(val, &clut->c_clut[regno]);
H A Dleo.c264 * @regno: boolean, 0 copy local, 1 get_user() function
271 static int leo_setcolreg(unsigned regno, argument
281 if (regno >= 256)
288 par->clut_data[regno] = red | (green << 8) | (blue << 16);
H A Dsh7760fb.c100 static int sh7760_setcolreg (u_int regno, argument
106 if (regno >= 16)
116 palette[regno] = (red << info->var.red.offset) |
H A Di740fb.c869 static int i740fb_setcolreg(unsigned regno, unsigned red, unsigned green, argument
875 dev_dbg(info->device, "setcolreg: regno: %i, red=%d, green=%d, blue=%d, transp=%d, bpp=%d\n",
876 regno, red, green, blue, transp, info->var.bits_per_pixel);
880 if (regno >= 256)
882 i740outb(info->par, VGA_PEL_IW, regno);
888 if (regno >= 16)
896 ((u32 *) info->pseudo_palette)[regno] = r | g | b;
/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_fb.c68 static int vmw_fb_setcolreg(unsigned regno, unsigned red, unsigned green, argument
75 if (regno > 15) {
76 DRM_ERROR("Bad regno %u.\n", regno);
83 pal[regno] = ((red & 0xff00) << 8) |
/drivers/video/fbdev/omap/
H A Dlcdc.c424 static int omap_lcdc_setcolreg(u_int regno, u16 red, u16 green, u16 blue, argument
429 if (lcdc.color_mode != OMAPFB_COLOR_CLUT_8BPP || regno > 255)
434 palette[regno] &= ~0x0fff;
435 palette[regno] |= ((red >> 12) << 8) | ((green >> 12) << 4 ) |
H A Domapfb.h188 int (*setcolreg) (u_int regno, u16 red, u16 green,
/drivers/video/fbdev/riva/
H A Dfbdev.c1291 * @regno: register index
1303 * Return != 0 for invalid regno.
1308 static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green, argument
1316 if (regno >= riva_get_cmap_len(&info->var))
1325 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1326 ((u32 *) info->pseudo_palette)[regno] =
1327 (regno << info->var.red.offset) |
1328 (regno << info->var.green.offset) |
1329 (regno << info->var.blue.offset);
1337 par->palette[regno]
[all...]
/drivers/gpu/drm/
H A Ddrm_fb_helper.c649 u16 blue, u16 regno, struct fb_info *info)
659 if (regno > 16)
673 palette[regno] = value;
685 pindex = regno;
688 pindex = regno << 3;
690 if (fb->depth == 16 && regno > 63)
692 if (fb->depth == 15 && regno > 31)
698 if (regno < 32) {
648 setcolreg(struct drm_crtc *crtc, u16 red, u16 green, u16 blue, u16 regno, struct fb_info *info) argument
/drivers/media/pci/ivtv/
H A Divtvfb.c871 static int ivtvfb_setcolreg(unsigned regno, unsigned red, unsigned green, argument
878 if (regno >= info->cmap.len)
883 write_reg(regno, 0x02a30);
885 itv->osd_info->palette_cur[regno] = color;
888 if (regno >= 16)
911 palette[regno] = color;
/drivers/video/fbdev/intelfb/
H A Dintelfbdrv.c143 static int intelfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1413 static int intelfb_setcolreg(unsigned regno, unsigned red, unsigned green, argument
1420 DBG_MSG("intelfb_setcolreg: regno %d, depth %d\n", regno, dinfo->depth);
1423 if (regno > 255)
1431 intelfbhw_setcolreg(dinfo, regno, red, green, blue,
1435 if (regno < 16) {
1438 dinfo->pseudo_palette[regno] = ((red & 0xf800) >> 1) |
1443 dinfo->pseudo_palette[regno] = (red & 0xf800) |
1448 dinfo->pseudo_palette[regno]
[all...]
/drivers/infiniband/hw/qib/
H A Dqib_iba6120.c299 * @regno: register number
307 enum qib_ureg regno, int ctxt)
313 return readl(regno + (u64 __iomem *)
317 return readl(regno + (u64 __iomem *)
326 * @regno: register number
333 enum qib_ureg regno, u64 value, int ctxt)
347 writeq(value, &ubase[regno]);
351 const u16 regno)
355 return readl((u32 __iomem *)&dd->kregbase[regno]);
359 const u16 regno)
306 qib_read_ureg32(const struct qib_devdata *dd, enum qib_ureg regno, int ctxt) argument
332 qib_write_ureg(const struct qib_devdata *dd, enum qib_ureg regno, u64 value, int ctxt) argument
350 qib_read_kreg32(const struct qib_devdata *dd, const u16 regno) argument
358 qib_read_kreg64(const struct qib_devdata *dd, const u16 regno) argument
367 qib_write_kreg(const struct qib_devdata *dd, const u16 regno, u64 value) argument
381 qib_write_kreg_ctxt(const struct qib_devdata *dd, const u16 regno, unsigned ctxt, u64 value) argument
388 write_6120_creg(const struct qib_devdata *dd, u16 regno, u64 value) argument
395 read_6120_creg(const struct qib_devdata *dd, u16 regno) argument
402 read_6120_creg32(const struct qib_devdata *dd, u16 regno) argument
[all...]
/drivers/gpu/drm/mgag200/
H A Dmgag200_mode.c1342 u16 blue, int regno)
1346 mga_crtc->lut_r[regno] = red >> 8;
1347 mga_crtc->lut_g[regno] = green >> 8;
1348 mga_crtc->lut_b[regno] = blue >> 8;
1353 u16 *blue, int regno)
1357 *red = (u16)mga_crtc->lut_r[regno] << 8;
1358 *green = (u16)mga_crtc->lut_g[regno] << 8;
1359 *blue = (u16)mga_crtc->lut_b[regno] << 8;
1341 mga_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, u16 blue, int regno) argument
1352 mga_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, u16 *blue, int regno) argument
/drivers/gpu/drm/radeon/
H A Dradeon_display.c213 u16 blue, int regno)
217 radeon_crtc->lut_r[regno] = red >> 6;
218 radeon_crtc->lut_g[regno] = green >> 6;
219 radeon_crtc->lut_b[regno] = blue >> 6;
224 u16 *blue, int regno)
228 *red = radeon_crtc->lut_r[regno] << 6;
229 *green = radeon_crtc->lut_g[regno] << 6;
230 *blue = radeon_crtc->lut_b[regno] << 6;
212 radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, u16 blue, int regno) argument
223 radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, u16 *blue, int regno) argument

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