Searched defs:control (Results 126 - 150 of 317) sorted by relevance

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/drivers/pinctrl/
H A Dpinctrl-as3722.c2 * ams AS3722 pin control and GPIO driver.
450 u32 control; local
455 ret = as3722_read(as3722, AS3722_GPIOn_CONTROL_REG(offset), &control);
462 invert_enable = !!(control & AS3722_GPIO_INV);
463 mode = control & AS3722_GPIO_MODE_MASK;
646 MODULE_DESCRIPTION("AS3722 pin control and GPIO driver");
/drivers/pnp/pnpbios/
H A Dpnpbios.h147 u16 control; /* system capabilities */ member in struct:pnp_bios_install_struct::__anon4871
/drivers/rtc/
H A Drtc-ds1343.c452 unsigned int control, stat; local
456 res = regmap_read(priv->map, DS1343_CONTROL_REG, &control);
464 control &= ~(DS1343_A0IE);
467 res = regmap_write(priv->map, DS1343_CONTROL_REG, control);
489 control |= DS1343_A0IE;
490 res = regmap_write(priv->map, DS1343_CONTROL_REG, control);
580 unsigned int stat, control; local
593 res = regmap_read(priv->map, DS1343_CONTROL_REG, &control);
597 control &= ~DS1343_A0IE;
598 regmap_write(priv->map, DS1343_CONTROL_REG, control);
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/drivers/staging/media/omap24xx/
H A Dtcm825x.c477 struct vcontrol *control; local
479 control = find_vctrl(qc->id);
481 if (control == NULL)
484 *qc = control->qc;
/drivers/usb/host/
H A Dsl811-hcd.c130 /* SETUP starts a new control request. Devices are not allowed to
131 * STALL or NAK these; they must cancel any pending control requests.
138 u8 control
158 control | SL11H_HCTLMASK_OUT);
163 /* STATUS finishes control requests, often after IN or OUT data packets */
169 u8 control
185 control |= SL11H_HCTLMASK_TOGGLE;
187 control |= SL11H_HCTLMASK_OUT;
188 sl811_write(sl811, bank + SL11H_HOSTCTLREG, control);
203 u8 control
306 u8 control; local
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/drivers/usb/musb/
H A Dmusb_dsps.c85 u16 control; member in struct:dsps_musb_wrapper
98 /* bit positions for control */
129 u32 control; member in struct:dsps_context
156 { "control", 0x14 },
449 r = platform_get_resource_byname(parent, IORESOURCE_MEM, "control");
472 dsps_writel(reg_base, wrp->control, (1 << wrp->reset));
482 * Check whether the dsps version has babble control enabled.
483 * In latest silicon revision the babble control logic is enabled.
484 * If MUSB_BABBLE_CTL returns 0x4 then we have the babble control
627 dsps_writel(musb->ctrl_base, wrp->control, (
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/drivers/usb/serial/
H A Dcp210x.c10 * Support to set flow control line levels using TIOCMGET and TIOCMSET
12 * control thanks to Munir Nassar nassarmu@real-time.com
476 * Reads the baud rate, data bits, parity, stop bits and flow control mode
604 dev_dbg(dev, "%s - flow control = CRTSCTS\n", __func__);
607 dev_dbg(dev, "%s - flow control = NONE\n", __func__);
766 dev_dbg(dev, "%s - flow control = CRTSCTS\n", __func__);
771 dev_dbg(dev, "%s - flow control = NONE\n", __func__);
792 unsigned int control = 0; local
795 control |= CONTROL_RTS;
796 control |
827 unsigned int control; local
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H A Dcypress_m8.c672 /* line control commands, which need to be executed immediately,
737 dev_dbg(dev, "%s - line control command being issued\n", __func__);
792 /* do not count the line control and size bytes */
821 __u8 status, control; local
826 control = priv->line_control;
830 result = ((control & CONTROL_DTR) ? TIOCM_DTR : 0)
831 | ((control & CONTROL_RTS) ? TIOCM_RTS : 0)
985 | IXON); /* disable enable XON/XOFF flow control */
1195 /* control and status byte(s) are also counted */
H A Doti6858.c36 * - test/implement flow control
77 /* format of the control packet */
97 u8 control; /* settings of flow control lines */ member in struct:oti6858_control_pkt
118 && ((a)->control == (priv)->pending_setup.control) \
183 u8 control; member in struct:oti6858_private::__anon7032
229 new_setup->control = priv->pending_setup.control;
408 u8 frame_fmt, control; local
589 u8 control; local
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H A Dpl2303.c470 u8 control; local
570 /* change control lines if we are switching to or from B0 */
572 control = priv->line_control;
577 if (control != priv->line_control) {
578 control = priv->line_control;
580 pl2303_set_control_lines(port, control);
601 u8 control; local
608 control = priv->line_control;
611 pl2303_set_control_lines(port, control);
661 u8 control; local
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/drivers/video/fbdev/
H A Dcg3.c83 u32 control; member in struct:bt_regs
89 u8 control; member in struct:cg3_regs
195 val = sbus_readb(&regs->control);
197 sbus_writeb(val, &regs->control);
205 val = sbus_readb(&regs->control);
207 sbus_writeb(val, &regs->control);
343 regp = (u8 __iomem *)&par->regs->cmap.control;
H A Dpxafb.h97 uint32_t control[2]; member in struct:pxafb_layer
H A Dtcx.c102 u32 control; member in struct:bt_regs
124 /* Reset control plane so that WID is 8-bit plane. */
446 sbus_writel(0xff << 24, &par->bt->control);
448 sbus_writel(0x00 << 24, &par->bt->control);
450 sbus_writel(0x73 << 24, &par->bt->control);
452 sbus_writel(0x00 << 24, &par->bt->control);
/drivers/vlynq/
H A Dvlynq.c66 u32 control; member in struct:vlynq_regs
124 writel(readl(&dev->local->control) | VLYNQ_CTRL_RESET,
125 &dev->local->control);
131 writel(readl(&dev->local->control) & ~VLYNQ_CTRL_RESET,
132 &dev->local->control);
278 val |= readl(&dev->local->control);
280 writel(val, &dev->local->control);
284 val |= readl(&dev->remote->control);
287 writel(val, &dev->remote->control);
402 writel((readl(&dev->remote->control)
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/drivers/block/
H A Dumem.c434 int control = le32_to_cpu(desc->sem_control_bits); local
438 if (!(control & DMASCR_DMA_COMPLETE)) {
439 control = dma_status;
455 (control & DMASCR_TRANSFER_READ) ?
457 if (control & DMASCR_HARD_ERROR) {
464 dump_dmastat(card, control);
927 /* Clear the LED's we control */
/drivers/char/ipmi/
H A Dipmi_smic_sm.c219 unsigned char control)
221 smic->io->outputb(smic->io, 1, control);
318 /* these are the control/status codes we actually use
218 write_smic_control(struct si_sm_data *smic, unsigned char control) argument
/drivers/clk/bcm/
H A Dclk-kona.c228 struct bcm_policy_ctl *control = &ccu->policy.control; local
234 /* If we don't need to control policy for this CCU, we're done. */
235 if (!policy_ctl_exists(control))
238 offset = control->offset;
239 go_bit = control->go_bit;
266 mask |= 1 << control->atl_bit;
268 mask |= 1 << control->ac_bit;
287 /* If we don't need to control policy for this CCU, we're done. */
420 /* For a hardware/software gate, set which is in control */
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H A Dclk-kona.h74 #define policy_ctl_exists(control) ((control)->offset != 0)
85 * CCU policy control for clocks. Clocks can be enabled or disabled
106 * Gating control and status is managed by a 32-bit gate register.
120 * under software control can be read from the gate status bit.
126 * under software or hardware control. Which type is in use is
141 * NO_DISABLE means this gate is (only) enabled if under software control
142 * SW_MANAGED means the status of this gate is under software control
147 #define BCM_CLK_GATE_FLAGS_SW ((u32)1 << 2) /* Software control */
149 #define BCM_CLK_GATE_FLAGS_SW_MANAGED ((u32)1 << 4) /* SW now in control */
466 struct bcm_policy_ctl control; member in struct:ccu_policy
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/drivers/i2c/busses/
H A Di2c-ismt.c157 u8 control; /* control bits */ member in struct:ismt_desc
190 /* Bus speed control bits for slow debuggers - refer to the docs for usage */
205 dev_dbg(dev, "\tcontrol= 0x%02X\n", desc->control);
399 /* Initialize common control bits */
401 desc->control = ISMT_DESC_INT | ISMT_DESC_FAIR;
403 desc->control = ISMT_DESC_FAIR;
407 desc->control |= ISMT_DESC_PEC;
421 desc->control |= ISMT_DESC_CWRL;
447 desc->control |
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H A Di2c-mv64xxx.c116 u8 control; member in struct:mv64xxx_i2c_regs
159 .control = 0x08,
169 .control = 0x0c,
292 drv_data->reg_base + drv_data->reg_offsets.control);
427 drv_data->reg_base + drv_data->reg_offsets.control);
462 drv_data->reg_base + drv_data->reg_offsets.control);
469 drv_data->reg_base + drv_data->reg_offsets.control);
476 drv_data->reg_base + drv_data->reg_offsets.control);
483 drv_data->reg_base + drv_data->reg_offsets.control);
490 drv_data->reg_base + drv_data->reg_offsets.control);
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/drivers/infiniband/hw/cxgb4/
H A Ddevice.c1458 static int c4iw_uld_control(void *handle, enum cxgb4_control control, ...) argument
1462 switch (control) {
1480 printk(KERN_WARNING MOD "%s: unknown control cmd %u\n",
1481 pci_name(ctx->lldi.pdev), control);
1492 .control = c4iw_uld_control,
/drivers/input/mouse/
H A Dsynaptics_i2c.c277 int ret, control; local
291 control = synaptics_i2c_reg_get(client, GENERAL_2D_CONTROL_REG);
293 control |= no_decel ? 1 << NO_DECELERATION : 0;
295 control |= reduce_report ? 1 << REDUCE_REPORTING : 0;
297 control |= no_filter ? 1 << NO_FILTER : 0;
298 ret = synaptics_i2c_reg_set(client, GENERAL_2D_CONTROL_REG, control);
/drivers/macintosh/
H A Dwindfarm_pm121.c2 * Windfarm PowerMac thermal control. iMac G5 iSight
17 * The algorithm used is the PID control algorithm, used the same way
25 * controls with a tiny difference. The control-ids of hard-drive-fan
36 * OD Fan control correction.
46 * HD Fan control correction.
56 * CPU Fan control correction.
70 * control value. The correction is computed in the following way :
74 * ref_value is the value of the reference control. If new_min is
81 * control : cpu-fan
87 * control
521 struct wf_control *control = NULL; local
595 struct wf_control *control; local
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/drivers/media/pci/ngene/
H A Dngene-core.c558 u8 control, u8 mode, u8 flags)
571 com.cmd.StreamControl.Stream = stream | (control ? 8 : 0);
574 com.cmd.StreamControl.Control = control |
587 if (!(control & 0x80)) {
709 u8 control = 0, mode = 0, flags = 0; local
739 control = 0x80;
758 control, mode, flags);
557 ngene_command_stream_control(struct ngene *dev, u8 stream, u8 control, u8 mode, u8 flags) argument
/drivers/media/platform/omap/
H A Domap_vout.c1360 ctrl->value = vout->control[0].value;
1378 ctrl->value = vout->control[2].value;
1419 vout->control[0].value = rotation;
1446 vout->control[1].value = color;
1470 vout->control[2].value = mirror;
1878 struct v4l2_control *control; local
1909 /*Initialize the control variables for
1911 control = vout->control;
1912 control[
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