Searched defs:base_addr (Results 51 - 75 of 113) sorted by relevance

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/drivers/net/ethernet/apm/xgene/
H A Dxgene_enet_main.c755 void __iomem *base_addr; local
768 pdata->base_addr = devm_ioremap_resource(dev, res);
769 if (IS_ERR(pdata->base_addr)) {
771 return PTR_ERR(pdata->base_addr);
831 base_addr = pdata->base_addr;
832 pdata->eth_csr_addr = base_addr + BLOCK_ETH_CSR_OFFSET;
833 pdata->eth_ring_if_addr = base_addr + BLOCK_ETH_RING_IF_OFFSET;
834 pdata->eth_diag_csr_addr = base_addr + BLOCK_ETH_DIAG_CSR_OFFSET;
837 pdata->mcx_mac_addr = base_addr
[all...]
H A Dxgene_enet_main.h116 void __iomem *base_addr; member in struct:xgene_enet_pdata
/drivers/net/wireless/ath/ath10k/
H A Dce.c855 "boot init ce src ring id %d entries %d base_addr %p\n",
889 "boot ce dest ring id %d entries %d base_addr %p\n",
901 dma_addr_t base_addr; local
923 &base_addr, GFP_KERNEL);
929 src_ring->base_addr_ce_space_unaligned = base_addr;
968 dma_addr_t base_addr; local
990 &base_addr, GFP_KERNEL);
996 dest_ring->base_addr_ce_space_unaligned = base_addr;
/drivers/spi/
H A Dspi-sun6i.c83 void __iomem *base_addr; member in struct:sun6i_spi
97 return readl(sspi->base_addr + reg);
102 writel(value, sspi->base_addr + reg);
119 byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
134 writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
368 sspi->base_addr = devm_ioremap_resource(&pdev->dev, res);
369 if (IS_ERR(sspi->base_addr)) {
370 ret = PTR_ERR(sspi->base_addr);
/drivers/staging/media/davinci_vpfe/
H A Ddm365_ipipe_hw.c27 static void ipipe_clock_enable(void *__iomem base_addr) argument
30 regw_ip(base_addr, IPIPE_GCK_MMR_DEFAULT, IPIPE_GCK_MMR);
33 regw_ip(base_addr, IPIPE_GCK_PIX_DEFAULT, IPIPE_GCK_PIX);
254 void __iomem *ipipe_base = ipipe->base_addr;
305 void *__iomem ipipe_base = vpfe_dev->vpfe_ipipe.base_addr;
306 void *__iomem rsz_base = vpfe_dev->vpfe_resizer.base_addr;
414 ipipe_set_lutdpc_regs(void *__iomem base_addr, void *__iomem isp5_base_addr, argument
422 ipipe_clock_enable(base_addr);
423 regw_ip(base_addr, dpc->en, DPC_LUT_EN);
429 regw_ip(base_addr, va
449 set_dpc_thresholds(void *__iomem base_addr, struct vpfe_ipipe_otfdpc_2_0_cfg *dpc_thr) argument
470 ipipe_set_otfdpc_regs(void *__iomem base_addr, struct vpfe_ipipe_otfdpc *otfdpc) argument
526 ipipe_set_d2f_regs(void *__iomem base_addr, unsigned int id, struct vpfe_ipipe_nf *noise_filter) argument
574 ipipe_set_gic_regs(void *__iomem base_addr, struct vpfe_ipipe_gic *gic) argument
612 ipipe_set_wb_regs(void *__iomem base_addr, struct vpfe_ipipe_wb *wb) argument
638 ipipe_set_cfa_regs(void *__iomem base_addr, struct vpfe_ipipe_cfa *cfa) argument
674 ipipe_set_rgb2rgb_regs(void *__iomem base_addr, unsigned int id, struct vpfe_ipipe_rgb2rgb *rgb) argument
741 ipipe_set_gamma_regs(void *__iomem base_addr, void *__iomem isp5_base_addr, struct vpfe_ipipe_gamma *gamma) argument
773 ipipe_set_3d_lut_regs(void *__iomem base_addr, void *__iomem isp5_base_addr, struct vpfe_ipipe_3d_lut *lut_3d) argument
822 ipipe_set_lum_adj_regs(void *__iomem base_addr, struct ipipe_lum_adj *lum_adj) argument
837 ipipe_set_rgb2ycbcr_regs(void *__iomem base_addr, struct vpfe_ipipe_rgb2yuv *yuv) argument
869 ipipe_set_yuv422_conv_regs(void *__iomem base_addr, struct vpfe_ipipe_yuv422_conv *conv) argument
882 ipipe_set_gbce_regs(void *__iomem base_addr, void *__iomem isp5_base_addr, struct vpfe_ipipe_gbce *gbce) argument
909 ipipe_set_ee_regs(void *__iomem base_addr, void *__iomem isp5_base_addr, struct vpfe_ipipe_yee *ee) argument
953 ipipe_set_mf(void *__iomem base_addr) argument
962 ipipe_set_gain_ctrl(void *__iomem base_addr, struct vpfe_ipipe_car *car) argument
978 ipipe_set_car_regs(void *__iomem base_addr, struct vpfe_ipipe_car *car) argument
1013 ipipe_set_cgs_regs(void *__iomem base_addr, struct vpfe_ipipe_cgs *cgs) argument
[all...]
H A Ddm365_isif.h162 void *__iomem base_addr; member in struct:isif_oper_config
H A Ddm365_resizer.h231 void *__iomem base_addr; member in struct:vpfe_resizer_device
/drivers/dma/
H A Dintel_mid_dma.c1232 u32 base_addr, bar_size; local
1266 base_addr = pci_resource_start(pdev, 0);
1268 device->dma_base = ioremap_nocache(base_addr, DMA_REG_SIZE);
H A Dfsl-edma.c647 void __iomem *base_addr; local
650 base_addr = fsl_edma->membase;
652 intr = edma_readl(fsl_edma, base_addr + EDMA_INTR);
659 base_addr + EDMA_CINT);
H A Dtegra20-apb-dma.c222 void __iomem *base_addr; member in struct:tegra_dma
234 writel(val, tdma->base_addr + reg);
239 return readl(tdma->base_addr + reg);
245 writel(val, tdc->tdma->base_addr + tdc->chan_base_offset + reg);
250 return readl(tdc->tdma->base_addr + tdc->chan_base_offset + reg);
1347 tdma->base_addr = devm_ioremap_resource(&pdev->dev, res);
1348 if (IS_ERR(tdma->base_addr))
1349 return PTR_ERR(tdma->base_addr);
/drivers/infiniband/hw/cxgb3/
H A Dcxio_hal.c129 setup.base_addr = 0; /* NULL address */
181 setup.base_addr = (u64) (cq->dma_addr);
197 setup.base_addr = (u64) (cq->dma_addr);
504 setup.base_addr = 0; /* NULL address */
518 u64 base_addr; local
553 base_addr = rdev_p->ctrl_qp.dma_addr;
554 base_addr >>= 12;
556 V_EC_BASE_LO((u32) base_addr & 0xffff));
559 base_addr >>= 16;
560 ctx1 = (u32) base_addr;
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/drivers/mfd/
H A Dlpc_ich.c874 u32 base_addr; local
881 base_addr = base_addr_cfg & 0x0000ff80;
882 if (!base_addr) {
889 res->start = base_addr + ACPIBASE_GPE_OFF;
890 res->end = base_addr + ACPIBASE_GPE_END;
907 base_addr = base_addr_cfg & 0x0000ff80;
908 if (!base_addr) {
916 res->start = base_addr;
951 u32 base_addr; local
957 base_addr
[all...]
/drivers/mtd/devices/
H A Dspear_smi.c191 * @base_addr: Base address of NOR-flash.
203 void __iomem *base_addr; member in struct:spear_snor_flash
566 src = flash->base_addr + from;
659 dest = flash->base_addr + to;
844 flash->base_addr = devm_ioremap(&pdev->dev, flash_info->mem_base,
846 if (!flash->base_addr)
/drivers/net/ethernet/qlogic/qlcnic/
H A Dqlcnic_init.c273 u32 base_addr, offset, pci_base; local
278 base_addr = addr & 0xfff00000;
282 if (crb_addr_xform[i] == base_addr) {
/drivers/net/ethernet/xilinx/
H A Dxilinx_emaclite.c110 * @base_addr: base address of the Emaclite device
129 void __iomem *base_addr; member in struct:net_local
161 reg_data = __raw_readl(drvdata->base_addr + XEL_TSR_OFFSET);
163 drvdata->base_addr + XEL_TSR_OFFSET);
166 __raw_writel(XEL_RSR_RECV_IE_MASK, drvdata->base_addr + XEL_RSR_OFFSET);
169 __raw_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET);
184 __raw_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET);
187 reg_data = __raw_readl(drvdata->base_addr + XEL_TSR_OFFSET);
189 drvdata->base_addr + XEL_TSR_OFFSET);
192 reg_data = __raw_readl(drvdata->base_addr
641 void __iomem *base_addr = lp->base_addr; local
[all...]
/drivers/net/fddi/
H A Ddefxx.c449 unsigned long base_addr = to_eisa_device(bdev)->base_addr; local
453 bar = inb(base_addr + PI_ESIC_K_MEM_ADD_CMP_2);
455 bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_CMP_1);
457 bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_CMP_0);
460 bar = inb(base_addr + PI_ESIC_K_MEM_ADD_MASK_2);
462 bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_MASK_1);
464 bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_MASK_0);
468 *bar_start = base_addr;
581 dev->base_addr
685 unsigned long base_addr = to_eisa_device(bdev)->base_addr; local
835 unsigned long base_addr = to_eisa_device(bdev)->base_addr; local
1921 unsigned long base_addr = to_eisa_device(bdev)->base_addr; local
[all...]
/drivers/parisc/
H A Ddino.c179 void __iomem *base_addr = d->hba.base_addr; local
182 DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devfn, where,
187 __raw_writel(v, base_addr + DINO_PCI_ADDR);
191 *val = readb(base_addr + DINO_CONFIG_DATA + (where & 3));
193 *val = readw(base_addr + DINO_CONFIG_DATA + (where & 2));
195 *val = readl(base_addr + DINO_CONFIG_DATA);
214 void __iomem *base_addr = d->hba.base_addr; local
217 DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devf
458 dino_card_setup(struct pci_bus *bus, void __iomem *base_addr) argument
[all...]
H A Dlba_pci.c208 error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); \
211 status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); \
217 arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK); \
223 WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK); \
229 WRITE_REG32(error_config | LBA_SMART_MODE, d->hba.base_addr + LBA_ERROR_CONFIG); \
238 WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\
243 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
248 WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA); \
253 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
308 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr
1639 void __iomem * base_addr = ioremap_nocache(lba->hpa.start, 4096); local
[all...]
/drivers/scsi/qla2xxx/
H A Dqla_tmpl.h81 uint32_t base_addr; member in struct:qla27xx_fwdt_entry::__packed::__packed
88 uint32_t base_addr; member in struct:qla27xx_fwdt_entry::__packed::__packed
95 uint32_t base_addr; member in struct:qla27xx_fwdt_entry::__packed::__packed
105 uint32_t base_addr; member in struct:qla27xx_fwdt_entry::__packed::__packed
/drivers/staging/netlogic/
H A Dxlr_net.c72 static inline void xlr_reg_update(u32 *base_addr, argument
77 tmp = xlr_nae_rdreg(base_addr, off);
78 xlr_nae_wreg(base_addr, off, (tmp & ~mask) | (val & mask));
306 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0,
309 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0 + 1,
312 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2, 0xffffffff);
313 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2 + 1, 0xffffffff);
314 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3, 0xffffffff);
315 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3 + 1, 0xffffffff);
317 xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFI
648 xlr_phy_write(u32 *base_addr, int phy_addr, int regnum, u16 val) argument
678 xlr_phy_read(u32 *base_addr, int phy_addr, int regnum) argument
[all...]
/drivers/video/fbdev/
H A Darcfb.c467 char *base_addr; local
469 base_addr = (char __force *)info->screen_base;
470 count -= copy_from_user(base_addr + p, buf, count);
/drivers/watchdog/
H A Dpcwd.c806 int base_addr = pcwd_ioports[id]; local
815 if (!request_region(base_addr, 4, "PCWD")) {
816 pr_info("Port 0x%04x unavailable\n", base_addr);
822 port0 = inb_p(base_addr); /* For REV A boards */
823 port1 = inb_p(base_addr + 1); /* For REV C boards */
833 port0 = inb_p(base_addr);
834 port1 = inb_p(base_addr + 1);
844 release_region(base_addr, 4);
/drivers/i2c/busses/
H A Di2c-eg20t.c741 void __iomem *base_addr; local
765 base_addr = pci_iomap(pdev, 1, 0);
767 if (base_addr == NULL) {
795 /* base_addr + offset; */
796 adap_info->pch_data[i].pch_base_address = base_addr + 0x100 * i;
819 pci_iounmap(pdev, base_addr);
/drivers/net/ethernet/cirrus/
H A Dep93xx_eth.c159 void __iomem *base_addr; member in struct:ep93xx_priv
182 #define rdb(ep, off) __raw_readb((ep)->base_addr + (off))
183 #define rdw(ep, off) __raw_readw((ep)->base_addr + (off))
184 #define rdl(ep, off) __raw_readl((ep)->base_addr + (off))
185 #define wrb(ep, off, val) __raw_writeb((val), (ep)->base_addr + (off))
186 #define wrw(ep, off, val) __raw_writew((val), (ep)->base_addr + (off))
187 #define wrl(ep, off, val) __raw_writel((val), (ep)->base_addr + (off))
792 if (ep->base_addr != NULL)
793 iounmap(ep->base_addr);
843 ep->base_addr
[all...]
/drivers/net/ethernet/dec/tulip/
H A Dwinbond-840.c322 void __iomem *base_addr; member in struct:netdev_private
410 np->base_addr = ioaddr;
570 void __iomem *mdio_addr = np->base_addr + MIICtrl;
600 void __iomem *mdio_addr = np->base_addr + MIICtrl;
632 void __iomem *ioaddr = np->base_addr;
741 void __iomem *ioaddr = np->base_addr;
782 void __iomem *ioaddr = np->base_addr;
836 iowrite32(np->ring_dma_addr, np->base_addr + RxRingPtr);
838 np->base_addr + TxRingPtr);
872 void __iomem *ioaddr = np->base_addr;
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