Searched refs:reg (Results 51 - 75 of 2563) sorted by relevance

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/drivers/net/wireless/rt2x00/
H A Drt2500usb.c62 __le16 reg; local
65 &reg, sizeof(reg), REGISTER_TIMEOUT);
66 *value = le16_to_cpu(reg);
73 __le16 reg; local
76 &reg, sizeof(reg), REGISTER_TIMEOUT);
77 *value = le16_to_cpu(reg);
94 __le16 reg = cpu_to_le16(value); local
97 &reg, sizeo
104 __le16 reg = cpu_to_le16(value); local
120 rt2500usb_regbusy_read(struct rt2x00_dev *rt2x00dev, const unsigned int offset, struct rt2x00_field16 field, u16 *reg) argument
149 u16 reg; local
172 u16 reg; local
203 u16 reg; local
280 u16 reg; local
293 u16 reg; local
311 u16 reg; local
346 u16 reg; local
424 u16 reg; local
457 u16 reg; local
495 u16 reg; local
651 u16 reg; local
696 u16 reg; local
742 u16 reg; local
765 u16 reg; local
790 u16 reg; local
1006 u16 reg; local
1148 u16 reg, reg0; local
1452 u16 reg; local
1774 u16 reg; local
[all...]
H A Drt2800mmio.c327 u32 reg; local
334 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, &reg);
335 rt2x00_set_field32(&reg, irq_field, 1);
336 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
367 u32 reg; local
379 rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
380 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
382 rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
384 rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
385 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVA
460 u32 reg, mask; local
516 u32 reg; local
559 u32 reg; local
612 u32 reg; local
808 u32 reg; local
[all...]
H A Drt61pci.c68 u32 reg; local
76 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
77 reg = 0;
78 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
79 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
80 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
81 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
83 rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg);
92 u32 reg; local
101 * doesn't become available in time, reg wil
123 u32 reg; local
149 u32 reg; local
177 u32 reg; local
192 u32 reg = 0; local
241 u32 reg; local
292 u32 reg; local
324 u32 reg; local
421 u32 reg; local
518 u32 reg; local
552 u32 reg; local
587 u32 reg; local
713 u32 reg; local
802 u32 reg; local
927 u32 reg; local
946 u32 reg; local
1011 u32 reg; local
1137 u32 reg; local
1160 u32 reg; local
1191 u32 reg; local
1296 u32 reg; local
1423 u32 reg; local
1504 u32 reg; local
1717 u32 reg; local
1773 u32 reg; local
1803 u32 reg, reg2; local
1973 u32 orig_reg, reg; local
2034 u32 orig_reg, reg; local
2161 u32 reg; local
2254 u32 reg; local
2272 u32 reg; local
2326 u32 reg, mask; local
2392 u32 reg; local
2502 u32 reg; local
2836 u32 reg; local
2903 u32 reg; local
2957 u32 reg; local
[all...]
H A Drt73usb.c66 u32 reg; local
74 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
75 reg = 0;
76 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
77 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
78 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
79 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
81 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
90 u32 reg; local
99 * doesn't become available in time, reg wil
121 u32 reg; local
186 u32 reg; local
239 u32 reg; local
271 u32 reg; local
368 u32 reg; local
468 u32 reg; local
502 u32 reg; local
536 u32 reg; local
698 u32 reg; local
810 u32 reg; local
829 u32 reg; local
886 u32 reg; local
1024 u32 reg; local
1047 u32 reg; local
1109 u32 reg; local
1151 u32 reg; local
1387 u32 reg, reg2; local
1535 u32 orig_reg, reg; local
1600 u32 orig_reg, reg; local
1857 u32 reg; local
2178 u32 reg; local
2240 u32 reg; local
2294 u32 reg; local
[all...]
/drivers/clk/berlin/
H A Dberlin2-avpll.c45 /* BG2/BG2CDs VCO_B has an additional shift of 4 for its VCO_CTRL0 reg */
127 u32 reg; local
129 reg = readl_relaxed(vco->base + VCO_CTRL0);
131 reg >>= 4;
133 return !!(reg & VCO_POWERUP);
139 u32 reg; local
141 reg = readl_relaxed(vco->base + VCO_CTRL0);
143 reg |= VCO_POWERUP << 4;
145 reg |= VCO_POWERUP;
146 writel_relaxed(reg, vc
154 u32 reg; local
170 u32 reg, refdiv, fbdiv; local
226 u32 reg; local
240 u32 reg; local
252 u32 reg; local
266 u32 reg, div_av2, div_av3, divider = 1; local
[all...]
/drivers/gpu/drm/i915/
H A Dintel_sideband.c102 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg) argument
107 SB_CRRDDA_NP, reg, &val);
112 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) argument
115 SB_CRWRDA_NP, reg, &val);
132 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg) argument
136 SB_CRRDDA_NP, reg, &val);
140 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) argument
143 SB_CRWRDA_NP, reg, &val);
146 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg) argument
150 SB_CRRDDA_NP, reg,
154 vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) argument
160 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg) argument
168 vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) argument
174 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg) argument
182 vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) argument
188 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg) argument
205 vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val) argument
212 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, enum intel_sbi_destination destination) argument
241 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, enum intel_sbi_destination destination) argument
270 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg) argument
278 vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) argument
[all...]
/drivers/net/ethernet/broadcom/genet/
H A Dbcmgenet_wol.c47 u32 reg; local
54 reg = bcmgenet_umac_readl(priv, UMAC_MPD_PW_MS);
55 put_unaligned_be16(reg, &wol->sopass[0]);
56 reg = bcmgenet_umac_readl(priv, UMAC_MPD_PW_LS);
57 put_unaligned_be32(reg, &wol->sopass[2]);
68 u32 reg; local
81 reg = bcmgenet_umac_readl(priv, UMAC_MPD_CTRL);
82 reg |= MPD_PW_EN;
83 bcmgenet_umac_writel(priv, reg, UMAC_MPD_CTRL);
130 u32 reg; local
186 u32 reg; local
[all...]
/drivers/mmc/host/
H A Dsdhci-bcm2835.c57 static void bcm2835_sdhci_writel(struct sdhci_host *host, u32 val, int reg) argument
59 writel(val, host->ioaddr + reg);
64 static inline u32 bcm2835_sdhci_readl(struct sdhci_host *host, int reg) argument
66 u32 val = readl(host->ioaddr + reg);
68 if (reg == SDHCI_CAPABILITIES)
74 static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val, int reg) argument
78 u32 oldval = (reg == SDHCI_COMMAND) ? bcm2835_host->shadow :
79 bcm2835_sdhci_readl(host, reg & ~3);
80 u32 word_num = (reg >> 1) & 1;
85 if (reg
91 bcm2835_sdhci_readw(struct sdhci_host *host, int reg) argument
101 bcm2835_sdhci_writeb(struct sdhci_host *host, u8 val, int reg) argument
112 bcm2835_sdhci_readb(struct sdhci_host *host, int reg) argument
[all...]
/drivers/media/platform/
H A Dindycam.c70 static int indycam_read_reg(struct v4l2_subdev *sd, u8 reg, u8 *value) argument
75 if (reg == INDYCAM_REG_RESET) {
77 "skipping write-only register %d\n", reg);
82 ret = i2c_smbus_read_byte_data(client, reg);
86 "register = 0x%02x\n", reg);
95 static int indycam_write_reg(struct v4l2_subdev *sd, u8 reg, u8 value) argument
100 if (reg == INDYCAM_REG_BRIGHTNESS || reg == INDYCAM_REG_VERSION) {
102 "skipping read-only register %d\n", reg);
106 dprintk("Writing Reg %d = 0x%02x\n", reg, valu
116 indycam_write_block(struct v4l2_subdev *sd, u8 reg, u8 length, u8 *data) argument
148 u8 reg; local
223 u8 reg; local
[all...]
/drivers/clk/mxs/
H A Dclk.c20 int mxs_clk_wait(void __iomem *reg, u8 shift) argument
24 while (readl_relaxed(reg) & (1 << shift))
H A Dclk.h24 int mxs_clk_wait(void __iomem *reg, u8 shift);
30 void __iomem *reg, u8 idx);
33 void __iomem *reg, u8 shift, u8 width, u8 busy);
36 void __iomem *reg, u8 shift, u8 width, u8 busy);
44 const char *parent_name, void __iomem *reg, u8 shift)
47 reg, shift, CLK_GATE_SET_TO_DISABLE,
51 static inline struct clk *mxs_clk_mux(const char *name, void __iomem *reg, argument
56 reg, shift, width, 0, &mxs_lock);
43 mxs_clk_gate(const char *name, const char *parent_name, void __iomem *reg, u8 shift) argument
/drivers/clk/sunxi/
H A Dclk-a20-gmac.c63 void __iomem *reg; local
83 reg = of_iomap(node, 0);
84 if (!reg)
88 gate->reg = reg;
91 mux->reg = reg;
112 iounmap(reg);
H A Dclk-factors.c39 #define FACTOR_GET(bit, len, reg) (((reg) & SETMASK(len, bit)) >> (bit))
41 #define FACTOR_SET(bit, len, reg, val) \
42 (((reg) & CLRMASK(len, bit)) | (val << (bit)))
48 u32 reg; local
54 reg = readl(factors->reg);
58 n = FACTOR_GET(config->nshift, config->nwidth, reg);
60 k = FACTOR_GET(config->kshift, config->kwidth, reg);
62 m = FACTOR_GET(config->mshift, config->mwidth, reg);
121 u32 reg; local
171 void __iomem *reg; local
[all...]
/drivers/hwmon/
H A Dadt7410.c16 static int adt7410_i2c_read_word(struct device *dev, u8 reg) argument
18 return i2c_smbus_read_word_swapped(to_i2c_client(dev), reg);
21 static int adt7410_i2c_write_word(struct device *dev, u8 reg, u16 data) argument
23 return i2c_smbus_write_word_swapped(to_i2c_client(dev), reg, data);
26 static int adt7410_i2c_read_byte(struct device *dev, u8 reg) argument
28 return i2c_smbus_read_byte_data(to_i2c_client(dev), reg);
31 static int adt7410_i2c_write_byte(struct device *dev, u8 reg, u8 data) argument
33 return i2c_smbus_write_byte_data(to_i2c_client(dev), reg, data);
H A Dlm75.h44 static inline int LM75_TEMP_FROM_REG(u16 reg) argument
48 return ((s16)reg / 128) * 500;
/drivers/media/pci/cx23885/
H A Dcx23885-ioctl.h28 struct v4l2_dbg_register *reg);
32 const struct v4l2_dbg_register *reg);
/drivers/net/ethernet/intel/i40evf/
H A Di40e_osdep.h45 #define wr32(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
46 #define rd32(a, reg) readl((a)->hw_addr + (reg))
48 #define wr64(a, reg, value) writeq((value), ((a)->hw_addr + (reg)))
49 #define rd64(a, reg) readq((a)->hw_addr + (reg))
/drivers/input/misc/
H A Dadxl34x-spi.c21 #define ADXL34X_WRITECMD(reg) (reg & 0x3F)
22 #define ADXL34X_READCMD(reg) (ADXL34X_CMD_READ | (reg & 0x3F))
23 #define ADXL34X_READMB_CMD(reg) (ADXL34X_CMD_READ | ADXL34X_CMD_MULTB \
24 | (reg & 0x3F))
26 static int adxl34x_spi_read(struct device *dev, unsigned char reg) argument
31 cmd = ADXL34X_READCMD(reg);
37 unsigned char reg, unsigned char val)
42 buf[0] = ADXL34X_WRITECMD(reg);
36 adxl34x_spi_write(struct device *dev, unsigned char reg, unsigned char val) argument
48 adxl34x_spi_read_block(struct device *dev, unsigned char reg, int count, void *buf) argument
[all...]
/drivers/phy/
H A Dphy-mvebu-sata.c35 u32 reg; local
40 reg = readl(priv->base + SATA_PHY_MODE_2);
41 reg |= (MODE_2_FORCE_PU_TX | MODE_2_FORCE_PU_RX |
43 writel(reg , priv->base + SATA_PHY_MODE_2);
46 reg = readl(priv->base + SATA_IF_CTRL);
47 reg &= ~CTRL_PHY_SHUTDOWN;
48 writel(reg, priv->base + SATA_IF_CTRL);
58 u32 reg; local
63 reg = readl(priv->base + SATA_PHY_MODE_2);
64 reg
[all...]
H A Dphy-qcom-ipq806x-sata.c64 u32 reg; local
67 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM3);
68 reg = reg | SATA_PHY_SSC_EN;
69 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM3);
71 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM0) &
75 reg |= SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3(0xf);
76 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM0);
78 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM1) &
82 reg |
119 u32 reg; local
[all...]
/drivers/mfd/
H A Dtps65912-core.c29 int tps65912_set_bits(struct tps65912 *tps65912, u8 reg, u8 mask) argument
36 err = tps65912->read(tps65912, reg, 1, &data);
38 dev_err(tps65912->dev, "Read from reg 0x%x failed\n", reg);
43 err = tps65912->write(tps65912, reg, 1, &data);
45 dev_err(tps65912->dev, "Write to reg 0x%x failed\n", reg);
53 int tps65912_clear_bits(struct tps65912 *tps65912, u8 reg, u8 mask) argument
59 err = tps65912->read(tps65912, reg, 1, &data);
61 dev_err(tps65912->dev, "Read from reg
76 tps65912_read(struct tps65912 *tps65912, u8 reg) argument
88 tps65912_write(struct tps65912 *tps65912, u8 reg, u8 val) argument
93 tps65912_reg_read(struct tps65912 *tps65912, u8 reg) argument
108 tps65912_reg_write(struct tps65912 *tps65912, u8 reg, u8 val) argument
[all...]
/drivers/pci/host/
H A Dpci-rcar-gen2.c98 void __iomem *reg; member in struct:rcar_pci_priv
130 iowrite32(val, priv->reg + RCAR_AHBPCI_WIN1_CTR_REG);
131 return priv->reg + (slot >> 1) * 0x100 + where;
137 void __iomem *reg = rcar_pci_cfg_base(bus, devfn, where); local
139 if (!reg)
144 *val = ioread8(reg);
147 *val = ioread16(reg);
150 *val = ioread32(reg);
160 void __iomem *reg = rcar_pci_cfg_base(bus, devfn, where); local
162 if (!reg)
238 void __iomem *reg = priv->reg; local
336 void __iomem *reg; local
[all...]
/drivers/pwm/
H A Dpwm-pca9685.c74 unsigned int reg; local
78 reg = PCA9685_ALL_LED_OFF_H;
80 reg = LED_N_OFF_H(pwm->hwpwm);
82 regmap_write(pca->regmap, reg, LED_FULL);
89 reg = PCA9685_ALL_LED_ON_H;
91 reg = LED_N_ON_H(pwm->hwpwm);
93 regmap_write(pca->regmap, reg, LED_FULL);
102 reg = PCA9685_ALL_LED_OFF_L;
104 reg = LED_N_OFF_L(pwm->hwpwm);
106 regmap_write(pca->regmap, reg, (in
121 unsigned int reg; local
158 unsigned int reg; local
[all...]
/drivers/media/tuners/
H A Dfc0012.c24 static int fc0012_writereg(struct fc0012_priv *priv, u8 reg, u8 val) argument
26 u8 buf[2] = {reg, val};
33 "%s: I2C write reg failed, reg: %02x, val: %02x\n",
34 KBUILD_MODNAME, reg, val);
40 static int fc0012_readreg(struct fc0012_priv *priv, u8 reg, u8 *val) argument
44 .buf = &reg, .len = 1 },
51 "%s: I2C read reg failed, reg: %02x\n",
52 KBUILD_MODNAME, reg);
69 unsigned char reg[] = { local
139 unsigned char reg[7], am, pm, multi, tmp; local
[all...]
/drivers/clk/mvebu/
H A Dclk-corediv.c57 void __iomem *reg; member in struct:clk_corediv
83 return !!(readl(corediv->reg) & enable_mask);
92 u32 reg; local
96 reg = readl(corediv->reg);
97 reg |= (BIT(desc->fieldbit) << soc_desc->enable_bit_offset);
98 writel(reg, corediv->reg);
111 u32 reg; local
115 reg
128 u32 reg, div; local
157 u32 reg, div; local
[all...]

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