Searched refs:ASYNC_BANK3_BASE (Results 1 - 15 of 15) sorted by relevance

/arch/blackfin/mach-bf518/include/mach/
H A Dmem_map.h16 #define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ macro
/arch/blackfin/mach-bf527/include/mach/
H A Dmem_map.h16 #define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ macro
/arch/blackfin/mach-bf538/include/mach/
H A Dmem_map.h16 #define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ macro
/arch/blackfin/mach-bf548/include/mach/
H A Dmem_map.h16 #define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */ macro
/arch/blackfin/mach-bf609/include/mach/
H A Dmem_map.h16 #define ASYNC_BANK3_BASE 0xBC000000 /* Async Bank 3 */ macro
/arch/blackfin/mach-bf533/include/mach/
H A Dmem_map.h16 #define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ macro
/arch/blackfin/mach-bf537/include/mach/
H A Dmem_map.h16 #define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ macro
/arch/blackfin/kernel/
H A Dprocess.c294 if (addr >= ASYNC_BANK3_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
297 if (addr + size <= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE)
H A Dsetup.c658 page_mask_nelts = (((_ramend + ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE -
H A Dtrace.c90 } else if (address >= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE && address < BOOT_ROM_START) {
/arch/blackfin/kernel/cplb-nompu/
H A Dcplbinit.c154 dcplb_bounds[i_d].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE;
193 icplb_bounds[i_i].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE;
H A Dcplbmgr.c203 && (addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE))
/arch/blackfin/include/asm/
H A Dmmu_context.h128 if (unlikely(addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE))
/arch/blackfin/mach-bf561/include/mach/
H A Dmem_map.h16 #define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */ macro
/arch/blackfin/kernel/cplb-mpu/
H A Dcplbmgr.c122 if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
221 if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {

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