Searched refs:DMA12_IRQ_STATUS (Results 1 - 6 of 6) sorted by relevance

/arch/blackfin/mach-bf538/include/mach/
H A DdefBF538.h503 #define DMA12_IRQ_STATUS 0xFFC01D28 /* DMA Channel 12 Interrupt/Status Register */ macro
H A DcdefBF538.h820 #define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS)
821 #define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
/arch/blackfin/mach-bf548/include/mach/
H A DdefBF54x_base.h706 #define DMA12_IRQ_STATUS 0xffc01c28 /* DMA Channel 12 Interrupt/Status Register */ macro
H A DcdefBF54x_base.h1181 #define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS)
1182 #define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
/arch/blackfin/mach-bf609/include/mach/
H A DcdefBF60x_base.h791 #define bfin_read_DMA12_IRQ_STATUS() bfin_read32(DMA12_IRQ_STATUS)
792 #define bfin_write_DMA12_IRQ_STATUS(val) bfin_write32(DMA12_IRQ_STATUS, val)
H A DdefBF60x_base.h1782 #define DMA12_IRQ_STATUS 0xFFC05130 /* DMA12 Status Register */ macro

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