Searched refs:RSI_CEATA_CONTROL (Results 1 - 5 of 5) sorted by relevance

/arch/blackfin/mach-bf518/include/mach/
H A DdefBF514.h33 #define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */ macro
H A DcdefBF514.h51 #define bfin_read_RSI_CEATA_CTL() bfin_read16(RSI_CEATA_CONTROL)
52 #define bfin_write_RSI_CEATA_CTL(val) bfin_write16(RSI_CEATA_CONTROL, val)
/arch/blackfin/kernel/
H A Ddebug-mmrs.c1374 D16(RSI_CEATA_CONTROL);
/arch/blackfin/mach-bf609/include/mach/
H A DcdefBF60x_base.h3223 #define bfin_read_RSI_CEATA_CONTROL() bfin_read16(RSI_CEATA_CONTROL)
3224 #define bfin_write_RSI_CEATA_CONTROL(val) bfin_write16(RSI_CEATA_CONTROL, val)
H A DdefBF60x_base.h54 #define RSI_CEATA_CONTROL 0xFFC0064C /* RSI0 This register contains bit to dis CCS gen */ macro

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