Searched refs:clk_set_rate (Results 1 - 25 of 51) sorted by relevance

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/arch/arm/mach-omap2/
H A Dclock3xxx.c63 clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
69 clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
H A Domap2-restart.c39 clk_set_rate(reset_virt_prcm_set_ck, rate);
/arch/arm/mach-pxa/
H A Dclock.c56 int clk_set_rate(struct clk *clk, unsigned long rate) function
69 EXPORT_SYMBOL(clk_set_rate); variable
/arch/arm/plat-versatile/
H A Dclock.c47 int clk_set_rate(struct clk *clk, unsigned long rate) function
54 EXPORT_SYMBOL(clk_set_rate); variable
/arch/arm/mach-omap1/
H A Dserial.c148 clk_set_rate(uart1_ck, 12000000);
158 clk_set_rate(uart2_ck, 12000000);
160 clk_set_rate(uart2_ck, 48000000);
170 clk_set_rate(uart3_ck, 12000000);
H A Dclock.h169 int (*clk_set_rate)(struct clk *clk, unsigned long rate); member in struct:clk_functions
/arch/arm/mach-s3c24xx/
H A Dcpufreq-utils.c65 clk_set_rate(cfg->mpll, cfg->pll.frequency);
/arch/arm/mach-mmp/
H A Dclock.c92 int clk_set_rate(struct clk *clk, unsigned long rate) function
105 EXPORT_SYMBOL(clk_set_rate); variable
/arch/mips/lantiq/
H A Dclk.c82 int clk_set_rate(struct clk *clk, unsigned long rate) function
100 EXPORT_SYMBOL(clk_set_rate); variable
/arch/mips/loongson/lemote-2f/
H A Dclock.c92 int clk_set_rate(struct clk *clk, unsigned long rate) function
124 EXPORT_SYMBOL_GPL(clk_set_rate); variable
/arch/sh/boards/
H A Dboard-apsh4ad0a.c109 ret = clk_set_rate(clk, 33333000);
H A Dboard-apsh4a3a.c131 ret = clk_set_rate(clk, 33333000);
H A Dboard-urquell.c196 ret = clk_set_rate(clk, 33333333);
/arch/arm/mach-imx/
H A Dclk-imx6sx.c510 clk_set_rate(clks[IMX6SX_CLK_EIM_SLOW], 132000000);
528 clk_set_rate(clks[IMX6SX_CLK_ENET_PODF], 200000000);
529 clk_set_rate(clks[IMX6SX_CLK_ENET_REF], 125000000);
530 clk_set_rate(clks[IMX6SX_CLK_ENET2_REF], 125000000);
533 clk_set_rate(clks[IMX6SX_CLK_PLL4_AUDIO_DIV], 393216000);
536 clk_set_rate(clks[IMX6SX_CLK_SPDIF_PODF], 98304000);
539 clk_set_rate(clks[IMX6SX_CLK_AUDIO_PODF], 24000000);
544 clk_set_rate(clks[IMX6SX_CLK_SSI1_PODF], 24576000);
545 clk_set_rate(clks[IMX6SX_CLK_SSI2_PODF], 24576000);
546 clk_set_rate(clk
[all...]
H A Dclk-vf610.c375 clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2);
376 clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2);
377 clk_set_rate(clk[VF610_CLK_QSPI0_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X2_DIV]) / 2);
380 clk_set_rate(clk[VF610_CLK_QSPI1_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_SEL]) / 2);
381 clk_set_rate(clk[VF610_CLK_QSPI1_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X4_DIV]) / 2);
382 clk_set_rate(clk[VF610_CLK_QSPI1_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X2_DIV]) / 2);
H A Dclk-imx51-imx53.c364 clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
365 clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
372 clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
441 clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000);
442 clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000);
548 clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
549 clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
559 clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
/arch/powerpc/platforms/512x/
H A Dmpc512x_shared.c143 clk_set_rate(clk_diu, want);
152 clk_set_rate(clk_diu, want);
173 clk_set_rate(clk_diu, pixclock);
/arch/arm/mach-mvebu/
H A Dplatsmp.c69 clk_set_rate(cpu_clk, rate);
/arch/avr32/mach-at32ap/
H A Dclock.c143 int clk_set_rate(struct clk *clk, unsigned long rate) function
157 EXPORT_SYMBOL(clk_set_rate); variable
/arch/mips/bcm63xx/
H A Dclk.c343 int clk_set_rate(struct clk *clk, unsigned long rate) function
347 EXPORT_SYMBOL_GPL(clk_set_rate); variable
/arch/sh/boards/mach-sdk7786/
H A Dsetup.c207 ret = clk_set_rate(clk, 33333333);
/arch/blackfin/mach-bf609/
H A Dclock.c124 int clk_set_rate(struct clk *clk, unsigned long rate) function
131 EXPORT_SYMBOL(clk_set_rate); variable
/arch/arm/mach-davinci/
H A Dclock.c157 int clk_set_rate(struct clk *clk, unsigned long rate) function
178 EXPORT_SYMBOL(clk_set_rate); variable
571 clk_set_rate(refclk, rate);
/arch/arm/mach-ep93xx/
H A Dclock.c469 int clk_set_rate(struct clk *clk, unsigned long rate) function
476 EXPORT_SYMBOL(clk_set_rate); variable
/arch/c6x/platforms/
H A Dpll.c109 int clk_set_rate(struct clk *clk, unsigned long rate) function
130 EXPORT_SYMBOL(clk_set_rate); variable

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