/arch/mips/sgi-ip22/ |
H A D | ip22-nvram.c | 55 static inline void eeprom_cmd(unsigned int *ctrl, unsigned cmd, unsigned reg) argument 63 __raw_writel(__raw_readl(ctrl) | EEPROM_DATO, ctrl); 65 __raw_writel(__raw_readl(ctrl) & ~EEPROM_DATO, ctrl); local 66 __raw_writel(__raw_readl(ctrl) & ~EEPROM_ECLK, ctrl); 68 __raw_writel(__raw_readl(ctrl) | EEPROM_ECLK, ctrl); 73 __raw_writel(__raw_readl(ctrl) 76 ip22_eeprom_read(unsigned int *ctrl, int reg) argument [all...] |
/arch/arm/kernel/ |
H A D | unwind.c | 223 static unsigned long unwind_get_byte(struct unwind_ctrl_block *ctrl) argument 227 if (ctrl->entries <= 0) { 232 ret = (*ctrl->insn >> (ctrl->byte * 8)) & 0xff; 234 if (ctrl->byte == 0) { 235 ctrl->insn++; 236 ctrl->entries--; 237 ctrl->byte = 3; 239 ctrl->byte--; 245 static int unwind_pop_register(struct unwind_ctrl_block *ctrl, argument 257 unwind_exec_pop_subset_r4_to_r13(struct unwind_ctrl_block *ctrl, unsigned long mask) argument 277 unwind_exec_pop_r4_to_rN(struct unwind_ctrl_block *ctrl, unsigned long insn) argument 297 unwind_exec_pop_subset_r0_to_r3(struct unwind_ctrl_block *ctrl, unsigned long mask) argument 319 unwind_exec_insn(struct unwind_ctrl_block *ctrl) argument 392 struct unwind_ctrl_block ctrl; local [all...] |
H A D | hw_breakpoint.c | 307 struct arch_hw_breakpoint_ctrl ctrl; local 313 memset(&ctrl, 0, sizeof(ctrl)); 314 ctrl.len = ARM_BREAKPOINT_LEN_8; 315 ctrl_reg = encode_ctrl_reg(ctrl); 339 u32 addr, ctrl; local 342 ctrl = encode_ctrl_reg(info->ctrl) | 0x1; 344 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) { 375 ctrl 477 arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl, int *gen_len, int *gen_type) argument 699 struct arch_hw_breakpoint_ctrl ctrl; local 804 struct arch_hw_breakpoint_ctrl ctrl; local [all...] |
/arch/mips/jz4740/ |
H A D | setup.c | 34 u32 ctrl, bus, bank, rows, cols; local 38 ctrl = readl(jz_emc_base + JZ4740_EMC_SDRAM_CTRL); 39 bus = 2 - ((ctrl >> 31) & 1); 40 bank = 1 + ((ctrl >> 19) & 1); 41 cols = 8 + ((ctrl >> 26) & 7); 42 rows = 11 + ((ctrl >> 20) & 3);
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/arch/arm/mach-omap1/ |
H A D | board-nand.c | 23 void omap1_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl) argument 31 mask = (ctrl & NAND_CLE) ? 0x02 : 0; 32 if (ctrl & NAND_ALE)
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/arch/arm64/include/asm/ |
H A D | hw_breakpoint.h | 32 struct arch_hw_breakpoint_ctrl ctrl; member in struct:arch_hw_breakpoint 35 static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl) argument 37 return (ctrl.len << 5) | (ctrl.type << 3) | (ctrl.privilege << 1) | 38 ctrl.enabled; 42 struct arch_hw_breakpoint_ctrl *ctrl) 44 ctrl->enabled = reg & 0x1; 46 ctrl->privilege = reg & 0x3; 48 ctrl 41 decode_ctrl_reg(u32 reg, struct arch_hw_breakpoint_ctrl *ctrl) argument [all...] |
/arch/cris/arch-v32/mm/ |
H A D | l2cache.c | 14 reg_l2cache_rw_ctrl ctrl = {0}; local 17 ctrl.csize = L2CACHE_SIZE; 18 ctrl.cbase = L2CACHE_SIZE / 4 + (L2CACHE_SIZE % 4 ? 1 : 0); 19 REG_WR(l2cache, regi_l2cache, rw_ctrl, ctrl);
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/arch/mips/kernel/ |
H A D | cevt-gt641xx.c | 51 u32 ctrl; local 55 ctrl = GT_READ(GT_TC_CONTROL_OFS); 56 ctrl &= ~(GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK); 57 ctrl |= GT_TC_CONTROL_ENTC0_MSK; 60 GT_WRITE(GT_TC_CONTROL_OFS, ctrl); 70 u32 ctrl; local 74 ctrl = GT_READ(GT_TC_CONTROL_OFS); 75 ctrl &= ~(GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK); 79 ctrl |= GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK; 82 ctrl | [all...] |
/arch/arm/include/asm/ |
H A D | hw_breakpoint.h | 24 struct arch_hw_breakpoint_ctrl ctrl; member in struct:arch_hw_breakpoint 27 static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl) argument 29 return (ctrl.mismatch << 22) | (ctrl.len << 5) | (ctrl.type << 3) | 30 (ctrl.privilege << 1) | ctrl.enabled; 34 struct arch_hw_breakpoint_ctrl *ctrl) 36 ctrl->enabled = reg & 0x1; 38 ctrl 33 decode_ctrl_reg(u32 reg, struct arch_hw_breakpoint_ctrl *ctrl) argument [all...] |
/arch/mips/lib/ |
H A D | iomap-pci.c | 16 struct pci_controller *ctrl = dev->bus->sysdata; local 17 unsigned long base = ctrl->io_map_base; 20 if (unlikely(!ctrl->io_map_base)) { 27 ctrl->io_map_base = base = mips_io_port_base; 40 return (void __iomem *) (ctrl->io_map_base + port);
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/arch/arm/mach-ks8695/ |
H A D | irq.c | 69 unsigned long ctrl, mode; local 72 ctrl = __raw_readl(KS8695_GPIO_VA + KS8695_IOPC); 98 ctrl &= ~IOPC_IOEINT0TM; 99 ctrl |= IOPC_IOEINT0_MODE(mode); 102 ctrl &= ~IOPC_IOEINT1TM; 103 ctrl |= IOPC_IOEINT1_MODE(mode); 106 ctrl &= ~IOPC_IOEINT2TM; 107 ctrl |= IOPC_IOEINT2_MODE(mode); 110 ctrl &= ~IOPC_IOEINT3TM; 111 ctrl | [all...] |
/arch/mips/oprofile/ |
H A D | op_model_loongson2.c | 37 unsigned int ctrl; member in struct:loongson2_register_config 54 unsigned int ctrl = 0; local 60 * Compute the performance counter ctrl word. 64 ctrl |= LOONGSON2_PERFCTRL_EVENT(0, cfg[0].event); 69 ctrl |= LOONGSON2_PERFCTRL_EVENT(1, cfg[1].event); 74 ctrl |= LOONGSON2_PERFCTRL_EXL | LOONGSON2_PERFCTRL_ENABLE; 76 ctrl |= LOONGSON2_PERFCTRL_KERNEL; 78 ctrl |= LOONGSON2_PERFCTRL_USER; 81 reg.ctrl = ctrl; [all...] |
/arch/powerpc/sysdev/ |
H A D | fsl_lbc.c | 188 static int fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl, argument 191 struct fsl_lbc_regs __iomem *lbc = ctrl->regs; 214 struct fsl_lbc_ctrl *ctrl = data; local 215 struct fsl_lbc_regs __iomem *lbc = ctrl->regs; 229 ctrl->irq_status = status; 232 dev_err(ctrl->dev, "Local bus monitor time-out: " 235 dev_err(ctrl->dev, "Write protect error: " 238 dev_err(ctrl->dev, "Atomic write error: " 241 dev_err(ctrl->dev, "Atomic read error: " 244 dev_err(ctrl 359 struct fsl_lbc_ctrl *ctrl = dev_get_drvdata(&pdev->dev); local 373 struct fsl_lbc_ctrl *ctrl = dev_get_drvdata(&pdev->dev); local [all...] |
/arch/powerpc/platforms/cell/ |
H A D | pervasive.c | 43 unsigned long ctrl, thread_switch_control; local 49 ctrl = mfspr(SPRN_CTRLF); 55 switch (ctrl & CTRL_CT) { 80 ctrl &= ~(CTRL_RUNLATCH | CTRL_TE); 81 mtspr(SPRN_CTRLT, ctrl);
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/arch/arm/boot/dts/ |
H A D | am3517.dtsi | 34 ti,davinci-ctrl-reg-offset = <0x10000>; 35 ti,davinci-ctrl-mod-reg-offset = <0>; 36 ti,davinci-ctrl-ram-offset = <0x20000>; 37 ti,davinci-ctrl-ram-size = <0x2000>;
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/arch/arm64/kernel/ |
H A D | hw_breakpoint.c | 234 enum debug_el dbg_el = debug_exception_level(info->ctrl.privilege); 235 u32 ctrl; local 237 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) { 271 ctrl = encode_ctrl_reg(info->ctrl); 273 reg_enable ? ctrl | 0x1 : ctrl & ~0x1); 335 len = get_hbp_len(info->ctrl.len); 345 int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl, argument 349 switch (ctrl 544 u32 ctrl; local 588 struct arch_hw_breakpoint_ctrl ctrl; local 665 struct arch_hw_breakpoint_ctrl ctrl; local [all...] |
/arch/arm/mach-lpc32xx/ |
H A D | irq.c | 212 unsigned int reg, ctrl, mask; local 214 get_controller(d->hwirq, &ctrl, &mask); 216 reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) & ~mask; 217 __raw_writel(reg, LPC32XX_INTC_MASK(ctrl)); 222 unsigned int reg, ctrl, mask; local 224 get_controller(d->hwirq, &ctrl, &mask); 226 reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) | mask; 227 __raw_writel(reg, LPC32XX_INTC_MASK(ctrl)); 232 unsigned int ctrl, mask; local 234 get_controller(d->hwirq, &ctrl, 247 unsigned int reg, ctrl, mask; local [all...] |
/arch/blackfin/include/asm/ |
H A D | cplb.h | 113 u32 ctrl = bfin_read32(mmr) & ~mask; local 116 bfin_write32(mmr, ctrl); 121 u32 ctrl = bfin_read32(mmr) & ~mask; local 123 bfin_write32(mmr, ctrl); 133 u32 ctrl = bfin_read32(mmr) | mask; local 136 bfin_write32(mmr, ctrl); 141 u32 ctrl = bfin_read32(mmr) | mask; local 143 bfin_write32(mmr, ctrl);
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/arch/cris/arch-v10/lib/ |
H A D | dmacopy.c | 25 indma.ctrl = d_eol | d_eop; 26 outdma.ctrl = d_eol;
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/arch/blackfin/mach-common/ |
H A D | cache-c.c | 45 u32 ctrl; local 48 ctrl = bfin_read32(mem_control) | (1 << RDCHK); 50 bfin_write32(mem_control, ctrl);
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/arch/cris/arch-v32/drivers/mach-a3/ |
H A D | nandflash.c | 51 unsigned int ctrl) 60 if (ctrl & NAND_CTRL_CHANGE) { 62 dout.regf_NCE = (ctrl & NAND_NCE) ? 0 : 1; 65 if (ctrl & NAND_ALE) { 69 } else if (ctrl & NAND_CLE) { 80 dout.regf_CLE = (ctrl & NAND_CLE) ? 1 : 0; 81 dout.regf_ALE = (ctrl & NAND_ALE) ? 1 : 0; 50 crisv32_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) argument
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/arch/sparc/kernel/ |
H A D | leon_kernel.c | 185 /* Used by external level sensitive IRQ handlers on the LEON: ACK IRQ ctrl */ 264 u32 rld, val, ctrl, off; local 268 ctrl = LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl); 269 if (LEON3_GPTIMER_CTRL_ISPENDING(ctrl)) { 314 u32 ctrl; local 387 ctrl = LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl); 388 LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl, 389 ctrl | LEON3_GPTIMER_CTRL_PENDIN 475 u32 ctrl; local [all...] |
/arch/arm/mach-ep93xx/ |
H A D | snappercl15.c | 50 unsigned int ctrl) 56 if (ctrl & NAND_CTRL_CHANGE) { 59 if (ctrl & NAND_NCE) 61 if (ctrl & NAND_CLE) 63 if (ctrl & NAND_ALE) 104 .ctrl = { 49 snappercl15_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) argument
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H A D | ts72xx.c | 75 int cmd, unsigned int ctrl) 79 if (ctrl & NAND_CTRL_CHANGE) { 86 bits |= (ctrl & NAND_NCE) << 2; /* bit 0 -> bit 2 */ 87 bits |= (ctrl & NAND_CLE); /* bit 1 -> bit 1 */ 88 bits |= (ctrl & NAND_ALE) >> 2; /* bit 2 -> bit 0 */ 137 .ctrl = { 74 ts72xx_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) argument
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/arch/cris/arch-v32/drivers/mach-fs/ |
H A D | nandflash.c | 50 unsigned int ctrl) 59 if (ctrl & NAND_CTRL_CHANGE) { 68 dout.data |= ((ctrl & CTRL_BITMASK) ^ NAND_NCE) << CE_BIT; 71 if (!(ctrl & NAND_NCE)) 73 if (ctrl & NAND_CLE) 75 if (ctrl & NAND_ALE) 49 crisv32_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) argument
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