/arch/mips/kvm/ |
H A D | locore.S | 61 /* k0/k1 not being used in host kernel context */ 62 INT_ADDIU k1, sp, -PT_SIZE 63 LONG_S $0, PT_R0(k1) 64 LONG_S $1, PT_R1(k1) 65 LONG_S $2, PT_R2(k1) 66 LONG_S $3, PT_R3(k1) 68 LONG_S $4, PT_R4(k1) 69 LONG_S $5, PT_R5(k1) 70 LONG_S $6, PT_R6(k1) 71 LONG_S $7, PT_R7(k1) [all...] |
/arch/sh/boards/mach-hp6xx/ |
H A D | pm_wakeup.S | 16 * k1 scratch 21 #define k1 r1 define 25 mov #-126, k1 27 mov.b k0, @k1 29 mov.l 5f, k1 31 mov.w k0, @k1 33 mov.l 4f, k1 34 jmp @k1
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/arch/mips/mm/ |
H A D | cex-oct.S | 31 PTR_LA k1, cache_err_dcache 33 PTR_ADDU k1, k0, k1 /* k1 = &cache_err_dcache[core_id] */ 36 sd k0, (k1) 40 mfc0 k1, CP0_STATUS 41 andi k1, k1, ST0_EXL 42 beqz k1, 1f
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H A D | cex-sb1.S | 48 * (0x170-0x17f) are used to preserve k0, k1, and ra. 55 * save/restore k0 and k1 from low memory (Useg is direct 62 sd k1,0x178($0) 72 mfc0 k1,C0_ERRCTL 73 bgtz k1,attempt_recovery 74 sll k0,k1,1 111 li k1,1 << 26 /* ICACHE_EXTERNAL */ 112 and k1,k0 113 bnez k1,unrecoverable 131 ld k1, [all...] |
H A D | cex-gen.S | 31 li k1,~CONF_CM_CMASK 32 and k0,k0,k1
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/arch/mips/kernel/ |
H A D | genex.S | 38 mfc0 k1, CP0_CAUSE 39 andi k1, k1, 0x7c 41 dsll k1, k1, 1 43 PTR_L k0, exception_handlers(k1) 58 mfc0 k1, CP0_CAUSE 60 andi k1, k1, 0x7c 64 beq k1, k [all...] |
H A D | bmips_vec.S | 42 li k1, CKSEG1 43 or k0, k1 58 mfc0 k1, $22, 3 59 srl k1, 16 60 andi k1, 0x8000 61 or k1, CKSEG1 | BMIPS_RELO_VECTOR_CONTROL_0 62 or k0, k1 63 li k1, 0xa0080000 64 sw k1, 0(k0) 70 li k1, CKSEG [all...] |
H A D | octeon_switch.S | 454 * safely modify k0 and k1. 466 v3mulu k1, $0, $0 469 sd k1, PT_MTP+8(sp) /* PT_MTP+8 has P1 */ 470 ori k1, $0, 1 471 v3mulu k1, k1, $0 474 sd k1, PT_MPL(sp) /* PT_MPL has MPL0 */ 475 v3mulu k1, $0, $0 478 sd k1, PT_MPL+16(sp) /* PT_MPL+16 has MPL2 */ 495 dmfc0 k1, [all...] |
H A D | pm-cps.c | 85 t8, t9, k0, k1, gp, sp, fp, ra, enumerator in enum:mips_reg
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/arch/mips/dec/prom/ |
H A D | locore.S | 20 la k1, mem_err 22 sw k0, 0(k1)
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/arch/mips/include/asm/ |
H A D | stackframe.h | 90 lui k1, %hi(kernelsp) variable 92 lui k1, %highest(kernelsp) 93 daddiu k1, %higher(kernelsp) 94 dsll k1, 16 95 daddiu k1, %hi(kernelsp) 96 dsll k1, 16 99 LONG_ADDU k1, k0 variable 100 LONG_L k1, %lo(kernelsp)(k1) variable 130 lui k1, 154 move k1, sp variable 160 PTR_SUBU sp, k1, PT_SIZE variable [all...] |
H A D | regdef.h | 54 #define k1 $27 macro 97 #define k1 $27 macro
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/arch/x86/include/asm/ |
H A D | rwsem.h | 108 " test " __ASM_SEL(%w1,%k1) "," __ASM_SEL(%w1,%k1) "\n\t" 133 " test " __ASM_SEL(%w1,%k1) "," __ASM_SEL(%w1,%k1) "\n\t" 142 " movzbl %b1, %k1\n\t"
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/arch/sh/kernel/cpu/sh3/ |
H A D | entry.S | 38 * ldc k1, ssr ! delay slot 72 #define k1 r1 define 86 * k1 scratch 261 mov #0xfffffff0, k1 262 extu.b k1, k1 263 not k1, k1 264 and k1, k2 ! Mask original SR value 307 ! k1 trashe [all...] |
H A D | swsusp.S | 17 #define k1 r1 define 118 mov.l 8f, k1 119 jsr @k1 ! switch to bank0 and save all regs
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/arch/arm64/crypto/ |
H A D | sha1-ce-core.S | 18 k1 .req v1 76 ld1r {k1.4s}, [x6], #4 106 add_update c, ev, k1, 8, 9, 10, 11 108 add_update p, od, k1, 9, 10, 11, 8 109 add_update p, ev, k1, 10, 11, 8, 9 110 add_update p, od, k1, 11, 8, 9, 10 111 add_update p, ev, k1, 8, 9, 10, 11
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/arch/mips/netlogic/common/ |
H A D | reset.S | 146 * We use scratch reg 6/7 to save k0/k1 and check for NMI first. 162 dmtc0 k1, $22, 7 164 li k1, 0x80000 165 and k1, k0, k1 166 beqz k1, 1f /* go to real reset entry */ 168 li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */ 169 ld k0, BOOT_NMI_HANDLER(k1)
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/arch/sh/kernel/cpu/shmobile/ |
H A D | sleep.S | 22 * k1 scratch 25 #define k1 r1 define 252 sts pr, k1 254 and k0, k1 257 ldc k1, vbr 260 mov.l @(SH_SLEEP_SR, k1), k0
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/arch/sparc/crypto/ |
H A D | des_glue.c | 206 u64 k1[DES_EXPKEY_WORDS / 2]; local 217 des_sparc64_key_expand((const u32 *)key, k1); 223 memcpy(&dctx->encrypt_expkey[0], &k1[0], sizeof(k1)); 232 &k1[0]);
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/arch/arm/boot/dts/ |
H A D | s3c6410-mini6410.dts | 77 button-k1 {
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/arch/ia64/kvm/ |
H A D | trampoline.S | 118 mov r17 = ar.k1; \ 155 mov ar.k1=r17; \
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