Searched refs:msr (Results 1 - 25 of 199) sorted by relevance

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/arch/x86/lib/
H A Dmsr.c3 #include <asm/msr.h>
5 struct msr *msrs_alloc(void)
7 struct msr *msrs = NULL;
9 msrs = alloc_percpu(struct msr);
19 void msrs_free(struct msr *msrs)
28 * @msr: MSR to read
35 int msr_read(u32 msr, struct msr *m) argument
40 err = rdmsrl_safe(msr, &val);
50 * @msr
53 msr_write(u32 msr, struct msr *m) argument
58 __flip_bit(u32 msr, u8 bit, bool set) argument
94 msr_set_bit(u32 msr, u8 bit) argument
107 msr_clear_bit(u32 msr, u8 bit) argument
[all...]
H A Dmsr-reg-export.c2 #include <asm/msr.h>
/arch/x86/kernel/cpu/
H A Dperfctr-watchdog.c43 /* converts an msr to an appropriate reservation bit */
44 static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr) argument
49 if (msr >= MSR_F15H_PERF_CTR)
50 return (msr - MSR_F15H_PERF_CTR) >> 1;
51 return msr - MSR_K7_PERFCTR0;
54 return msr - MSR_ARCH_PERFMON_PERFCTR0;
58 return msr - MSR_P6_PERFCTR0;
60 return msr - MSR_KNC_PERFCTR0;
62 return msr - MSR_P4_BPU_PERFCTR0;
69 * converts an msr t
72 nmi_evntsel_msr_to_bit(unsigned int msr) argument
106 reserve_perfctr_nmi(unsigned int msr) argument
121 release_perfctr_nmi(unsigned int msr) argument
134 reserve_evntsel_nmi(unsigned int msr) argument
149 release_evntsel_nmi(unsigned int msr) argument
[all...]
/arch/powerpc/include/asm/
H A Drunlatch.h21 unsigned long msr = mfmsr(); \
24 if (msr & MSR_EE) \
33 unsigned long msr = mfmsr(); \
36 if (msr & MSR_EE) \
H A Dperf_event.h38 asm volatile("mfmsr %0" : "=r" ((regs)->msr)); \
H A Dprobes.h50 regs->msr |= MSR_SINGLESTEP;
57 regs->msr &= ~MSR_CE;
H A Dhw_irq.h176 unsigned long msr = mfmsr();
177 SET_MSR_EE(msr | MSR_EE);
195 return !(regs->msr & MSR_EE);
/arch/microblaze/kernel/
H A Dprocess.c43 pr_info(" msr=%08lX, ear=%08lX, esr=%08lX, fsr=%08lX\n",
44 regs->msr, regs->ear, regs->esr, regs->fsr);
69 local_save_flags(childregs->msr);
71 ti->cpu_context.msr = childregs->msr & ~MSR_IE;
83 ti->cpu_context.msr = (unsigned long)childregs->msr;
85 childregs->msr |= MSR_UMS;
97 childregs->msr &= ~MSR_EIP;
98 childregs->msr |
[all...]
/arch/m68k/bvme6000/
H A Dconfig.c164 unsigned char msr = rtc->msr & 0xc0; local
166 rtc->msr = msr | 0x20; /* Ack the interrupt */
183 unsigned char msr = rtc->msr & 0xc0; local
185 rtc->msr = 0; /* Ensure timer registers accessible */
196 rtc->msr = 0x40; /* Access int.cntrl, etc */
201 rtc->msr = 0; /* Access timer 1 control */
204 rtc->msr
225 unsigned char msr = rtc->msr & 0xc0; local
272 unsigned char msr = rtc->msr & 0xc0; local
323 unsigned char msr = rtc->msr & 0xc0; local
[all...]
H A Drtc.c41 unsigned char msr; local
51 msr = rtc->msr & 0xc0;
52 rtc->msr = 0x40;
65 rtc->msr = msr;
107 msr = rtc->msr & 0xc0;
108 rtc->msr = 0x40;
122 rtc->msr
[all...]
/arch/x86/include/asm/
H A Dmsr.h4 #include <uapi/asm/msr.h>
12 struct msr { struct
24 struct msr reg;
25 struct msr *msrs;
60 static inline unsigned long long native_read_msr(unsigned int msr) argument
64 asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr));
68 static inline unsigned long long native_read_msr_safe(unsigned int msr, argument
80 : "c" (msr), [fault] "i" (-EIO));
84 static inline void native_write_msr(unsigned int msr, argument
87 asm volatile("wrmsr" : : "c" (msr), "
91 native_write_msr_safe(unsigned int msr, unsigned low, unsigned high) argument
147 wrmsr(unsigned msr, unsigned low, unsigned high) argument
159 wrmsr_safe(unsigned msr, unsigned low, unsigned high) argument
174 rdmsrl_safe(unsigned msr, unsigned long long *p) argument
[all...]
H A Dmicrocode.h4 #define native_rdmsr(msr, val1, val2) \
6 u64 __val = native_read_msr((msr)); \
11 #define native_wrmsr(msr, low, high) \
12 native_write_msr(msr, low, high)
14 #define native_wrmsrl(msr, val) \
15 native_write_msr((msr), \
/arch/x86/include/uapi/asm/
H A Dmsr.h4 #include <asm/msr-index.h>
/arch/x86/kernel/
H A Dtrace_clock.c6 #include <asm/msr.h>
/arch/arm64/include/asm/
H A Dassembler.h42 msr daifset, #2
46 msr daifclr, #2
58 msr daif, \olddaif
65 msr daifset, #8
69 msr daifclr, #8
76 msr mdscr_el1, \tmp
86 msr mdscr_el1, \tmp
96 msr daifclr, #(8 | 2)
/arch/arm64/kvm/
H A Dhyp.S75 msr sp_el1, x22
76 msr elr_el1, x23
77 msr spsr_el1, x24
83 msr sp_el0, x19
84 msr elr_el2, x20 // EL1 PC
85 msr spsr_el2, x21 // EL1 pstate
443 msr vmpidr_el2, x4
444 msr csselr_el1, x5
445 msr sctlr_el1, x6
446 msr actlr_el
[all...]
H A Dhyp-init.S61 msr ttbr0_el2, x0
68 msr tcr_el2, x4
77 msr vtcr_el2, x4
80 msr mair_el2, x4
91 msr sctlr_el2, x4
101 msr ttbr0_el2, x1
112 msr vbar_el2, x3
/arch/arm/common/
H A Dfiq_glue.S56 msr cpsr_c, r4
67 msr cpsr_c, #(SVC_MODE | PSR_I_BIT | PSR_F_BIT)
80 msr cpsr_c, r4
83 msr spsr_cxsf, r5
86 msr cpsr_c, #(FIQ_MODE | PSR_I_BIT | PSR_F_BIT)
93 msr spsr_cxsf, r12
108 msr cpsr_c, #(FIQ_MODE | PSR_I_BIT | PSR_F_BIT)
115 msr cpsr_c, r4
/arch/arm64/mm/
H A Dproc.S56 msr sctlr_el1, x0
74 msr sctlr_el1, x1 // disable the MMU
152 msr tpidr_el0, x2
153 msr tpidrro_el0, x3
154 msr contextidr_el1, x4
155 msr mair_el1, x5
156 msr cpacr_el1, x6
157 msr ttbr0_el1, x1
158 msr ttbr1_el1, x7
159 msr tcr_el
[all...]
/arch/arm/kernel/
H A Dfiqasm.S28 msr cpsr_c, r2 @ select FIQ mode
33 msr cpsr_c, r1 @ return to SVC mode
41 msr cpsr_c, r2 @ select FIQ mode
46 msr cpsr_c, r1 @ return to SVC mode
/arch/powerpc/kernel/
H A Dsignal_64.c95 unsigned long msr = regs->msr; local
110 msr |= MSR_VEC;
129 msr &= ~MSR_VSX;
143 msr |= MSR_VSX;
149 err |= __put_user(msr, &sc->gp_regs[PT_MSR]);
189 unsigned long msr = regs->msr; local
192 BUG_ON(!MSR_TM_ACTIVE(regs->msr));
199 regs->msr
309 unsigned long msr; local
408 unsigned long msr; local
665 unsigned long msr; local
[all...]
H A Dsignal_32.c412 unsigned long msr = regs->msr; local
430 msr |= MSR_VEC;
432 /* else assert((regs->msr & MSR_VEC) == 0) */
452 msr &= ~MSR_VSX;
464 msr |= MSR_VSX;
476 msr |= MSR_SPE;
478 /* else assert((regs->msr & MSR_SPE) == 0) */
485 if (__put_user(msr, &frame->mc_gregs[PT_MSR]))
519 unsigned long msr local
667 unsigned long msr; local
777 unsigned long msr, msr_hi; local
[all...]
H A Dprocess.c87 MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
89 tsk->thread.tm_orig_msr = tsk->thread.regs->msr;
105 MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
107 tsk->thread.tm_orig_msr = tsk->thread.regs->msr;
129 * another process could get scheduled after the regs->msr
136 if (tsk->thread.regs->msr & MSR_FP) {
160 if (current->thread.regs && (current->thread.regs->msr & MSR_FP))
176 if (current->thread.regs && (current->thread.regs->msr & MSR_VEC))
194 if (tsk->thread.regs->msr & MSR_VEC) {
214 if (current->thread.regs && (current->thread.regs->msr
649 unsigned long msr; local
[all...]
/arch/powerpc/platforms/pasemi/
H A Didle.c52 if (regs->msr & SRR1_WAKEMASK)
55 switch (regs->msr & SRR1_WAKEMASK) {
71 regs->msr |= MSR_RI;
/arch/microblaze/include/asm/
H A Dsetup.h39 unsigned int fdt, unsigned int msr, unsigned int tlb0,

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